Low-power SRAM design using half-swing pulse-mode techniques. - Kenneth W. Mai; Toshihiko Mori; Bharadwaj S. Amrutur; Ron Ho; Bennett Wilburn; Mark A. Horowitz; Isao Fukushi; Tetsuo Izawa; Shin Mitarai (IEEE J. Solid State Circuits, 1998)

Interconnect scaling implications for CAD. - Ron Ho; Ken Mai; Hema Kapadia; Mark Horowitz (ICCAD, 1999)

Smart Memories: a modular reconfigurable architecture. - Ken Mai; Tim Paaske; Nuwan Jayasena; Ron Ho; William J. Dally; Mark Horowitz (ISCA, 2000)

The future of wires. - Ron Ho; Kenneth Mai; Mark A. Horowitz (Proc. IEEE, 2001)

Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. - Ken Mai; Ron Ho; Elad Alon; Dean Liu; Younggon Kim; Dinesh Patil; Mark A. Horowitz (IEEE J. Solid State Circuits, 2005)

PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. - Eric S. Chung; Eriko Nurvitadhi; James C. Hoe; Babak Falsafi; Ken Mai (IPDPS, 2007)

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. - Jangwoo Kim; Nikos Hardavellas; Ken Mai; Babak Falsafi; James C. Hoe (MICRO, 2007)

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. - Umut Arslan; Mark P. McCartney; Mudit Bhargava; Xin Li 001; Ken Mai; Lawrence T. Pileggi (CICC, 2008)

Mismatch analysis and statistical design at 65 nm and below. - Larry T. Pileggi; Gökçe Keskin; Xin Li 001; Ken Mai; Jonathan E. Proesel (CICC, 2008)

A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. - Eric S. Chung; Eriko Nurvitadhi; James C. Hoe; Babak Falsafi; Ken Mai (FPGA, 2008)

A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style. - Eric Menendez; Ken Mai (HOST, 2008)

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. - Benton H. Calhoun; Yu Cao 001; Xin Li 001; Ken Mai; Lawrence T. Pileggi; Rob A. Rutenbar; Kenneth L. Shepard (Proc. IEEE, 2008)

Low-overhead, digital offset compensated, SRAM sense amplifiers. - Mudit Bhargava; Mark P. McCartney; Alexander Hoefler; Ken Mai (CICC, 2009)

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. - Satyanand Nalam; Mudit Bhargava; Kyle Ringgenberg; Ken Mai; Benton H. Calhoun (ICCD, 2009)

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. - Eric S. Chung; Michael Papamichael; Eriko Nurvitadhi; James C. Hoe; Ken Mai; Babak Falsafi (ACM Trans. Reconfigurable Technol. Syst., 2009)

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. - Satyanand Nalam; Mudit Bhargava; Ken Mai; Benton H. Calhoun (DAC, 2010)

Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. - Mudit Bhargava; Cagla Cakir; Ken Mai (HOST, 2010)

A Comparison of Power-analysis-resistant Digital Circuits. - Eric Menendez; Ken Mai (HOST, 2010)

Side-channel Attack Resistant ROM-based AES S-Box. - Craig Teegarden; Mudit Bhargava; Ken Mai (HOST, 2010)

Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? - Eric S. Chung; Peter A. Milder; James C. Hoe; Ken Mai (MICRO, 2010)

Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems. - David S. Ricketts; James A. Bain; Yi Luo; Ronald D. Blanton; Kenneth Mai; Gary K. Fedder (Proc. IEEE, 2010)

FPGA-Based Solid-State Drive Prototyping Platform. - Yu Cai 001; Erich F. Haratsch; Mark P. McCartney; Ken Mai (FCCM, 2011)

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). - Yu Cai 001; Erich F. Haratsch; Mark P. McCartney; Mudit Bhargava; Ken Mai (FPGA, 2011)

CoRAM: an in-fabric memory architecture for FPGA-based computing. - Eric S. Chung; James C. Hoe; Ken Mai (FPGA, 2011)

Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. - Mudit Bhargava; Cagla Cakir; Ken Mai (CICC, 2012)

6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. - Cagla Cakir; Mudit Bhargava; Ken Mai (CICC, 2012)

Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. - Yu Cai 001; Erich F. Haratsch; Onur Mutlu; Ken Mai (DATE, 2012)

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. - Eric S. Chung; Michael Papamichael; Gabriel Weisz; James C. Hoe; Ken Mai (FPGA, 2012)

Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. - Mudit Bhargava; Cagla Cakir; Ken Mai (HOST, 2012)

Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. - Yu Cai 001; Gulay Yalcin; Onur Mutlu; Erich F. Haratsch; Adrián Cristal; Osman S. Ünsal; Ken Mai (ICCD, 2012)

Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. - Yu Cai 001; Erich F. Haratsch; Onur Mutlu; Ken Mai (DATE, 2013)

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. - Yu Cai 001; Onur Mutlu; Erich F. Haratsch; Ken Mai (ICCD, 2013)

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. - Ben Niewenhuis; Ronald D. Blanton; Mudit Bhargava; Ken Mai (ITC, 2013)

Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. - Jangwoo Kim; Hyunggyun Yang; Mark P. McCartney; Mudit Bhargava; Ken Mai; Babak Falsafi (PRDC, 2013)

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. - Mudit Bhargava; Ken Mai (DATE, 2014)

SLIC: Statistical learning in chip. - Ronald D. Blanton; Xin Li 001; Ken Mai; Diana Marculescu; Radu Marculescu; Jeyanandh Paramesh; Jeff G. Schneider; Donald E. Thomas (ISIC, 2014)

Neighbor-cell assisted error correction for MLC NAND flash memories. - Yu Cai 001; Gulay Yalcin; Onur Mutlu; Erich F. Haratsch; Osman S. Unsal; Adrián Cristal; Ken Mai (SIGMETRICS, 2014)

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. - Burak Erbagci; Fangfei Liu; Cagla Cakir; Nail Etkin Can Akkaya; Ruby B. Lee; Ken Mai (A-SSCC, 2015)

A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm. - Burak Erbagci; Nail Etkin Can Akkaya; Craig Teegarden; Ken Mai (CICC, 2015)

A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. - Nail Etkin Can Akkaya; Burak Erbagci; Raymond Carley; Ken Mai (HOST, 2015)

Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. - Mudit Bhargava; Kaship Sheikh; Ken Mai (HOST, 2015)

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. - Yu Cai 001; Yixin Luo; Erich F. Haratsch; Ken Mai; Onur Mutlu (HPCA, 2015)

Statistical Learning in Chip (SLIC). - Ronald D. Blanton; Xin Li 001; Ken Mai; Diana Marculescu; Radu Marculescu; Jeyanandh Paramesh; Jeff G. Schneider; Donald E. Thomas (ICCAD, 2015)

High-efficiency crossbar switches using capacitively coupled signaling. - Cagla Cakir; Ron Ho; Jon K. Lexau; Ken Mai (ISLPED, 2015)

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. - Michael Papamichael; Cagla Cakir; Chen Sun 003; Chia-Hsin Owen Chen; James C. Hoe; Ken Mai; Li-Shiuan Peh; Vladimir Stojanovic (ISPASS, 2015)

Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks. - Yu Cai 001; Ken Mai; Onur Mutlu (ISQED, 2015)

Modeling and Design of High-Radix On-Chip Crossbar Switches. - Cagla Cakir; Ron Ho; Jon K. Lexau; Ken Mai (NOCS, 2015)

Deeply hardware-entangled reconfigurable logic and interconnect. - Burak Erbagci; Mudit Bhargava; Rachel Dondero; Ken Mai (ReConFig, 2015)

A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. - Mudit Bhargava; Ken Mai (IACR Cryptol. ePrint Arch., 2015)

Guest Editorial Special Section on Hardware Security and Trust. - Ramesh Karri; Farinaz Koushanfar; Ozgur Sinanoglu; Yiorgos Makris; Ken Mai; Ahmad-Reza Sadeghi; Swarup Bhunia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A secure camouflaged threshold voltage defined logic family. - Burak Erbagci; Cagri Erbagci; Nail Etkin Can Akkaya; Ken Mai (HOST, 2016)

Scalable High-Radix Modular Crossbar Switches. - Cagla Cakir; Ron Ho; Jon K. Lexau; Ken Mai (Hot Interconnects, 2016)

Technologies for secure RFID authentication of medicinal pills and capsules. - L. Richard Carley; Gurkan Colak; Louis Chomas; Larry T. Pileggi; Kenneth Mai (RFID-TA, 2016)

Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks. - Fangfei Liu; Hao Wu; Kenneth Mai; Ruby B. Lee (IEEE Micro, 2016)

Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. - Yu Cai 001; Saugata Ghose; Yixin Luo; Ken Mai; Onur Mutlu; Erich F. Haratsch (HPCA, 2017)

Secure chip odometers using intentional controlled aging. - Nail Etkin Can Akkaya; Burak Erbagci; Ken Mai (HOST, 2018)

A compact energy-efficient pseudo-static camouflaged logic family. - Prashanth Mohan; Nail Etkin Can Akkaya; Burak Erbagci; Ken Mai (HOST, 2018)

A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD. - Nail Etkin Can Akkaya; Burak Erbagci; Ken Mai (ISSCC, 2018)

Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory. - Yu Cai 001; Yixin Luo; Erich F. Haratsch; Ken Mai; Saugata Ghose; Onur Mutlu (CoRR, 2018)

Read Disturb Errors in MLC NAND Flash Memory. - Yu Cai 001; Yixin Luo; Saugata Ghose; Erich F. Haratsch; Ken Mai; Onur Mutlu (CoRR, 2018)

Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming. - Yu Cai 001; Saugata Ghose; Yixin Luo; Ken Mai; Onur Mutlu; Erich F. Haratsch (CoRR, 2018)

An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS. - Burak Erbagci; Nail Etkin Can Akkaya; Cagri Erbagci; Ken Mai (ESSCIRC, 2019)

Secure hardware-entangled field programmable gate arrays. - Burak Erbagci; Nail Etkin Can Akkaya; Mudit Bhargava; Rachel Dondero; Ken Mai (J. Parallel Distributed Comput., 2019)

A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. - Prashanth Mohan; Oguz Atli; Onur O. Kibar; Ken Mai (FPGA, 2020)

ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS. - Prashanth Mohan; Wen Wang 007; Bernhard Jungk; Ruben Niederhagen; Jakub Szefer; Ken Mai (ICCD, 2020)

Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. - Prashanth Mohan; Oguz Atli; Joseph Sweeney; Onur O. Kibar; Larry T. Pileggi; Ken Mai (DATE, 2021)

Top-down Physical Design of Soft Embedded FPGA Fabrics. - Prashanth Mohan; Oguz Atli; Onur O. Kibar; V. Mohammed Zackriya; Larry T. Pileggi; Ken Mai (FPGA, 2021)

Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture. - Graham Gobieski; Ahmet Oguz Atli; Kenneth Mai; Brandon Lucia; Nathan Beckmann (ISCA, 2021)

Split-Chip Design to Prevent IP Reverse Engineering. - Samuel Pagliarini; Joseph Sweeney; Ken Mai; R. D. Shawn Blanton; Larry T. Pileggi; Subhasish Mitra (IEEE Des. Test, 2021)

A High Throughput Hardware Accelerator for FFTW Codelets: A First Look. - Larry T. Pileggi; Siyuan Chen; Keshav Harisrikanth; Guanglin Xu; Ken Mai; Franz Franchetti (HPEC, 2022)

Towards Specialized Hardware for Learning-based Visual Odometry on the Edge. - Siyuan Chen; Ken Mai (IROS, 2022)

Logic Locking - Connecting Theory and Practice. - Elisaweta Masserova; Deepali Garg; Ken Mai; Lawrence T. Pileggi; Vipul Goyal; Bryan Parno (IACR Cryptol. ePrint Arch., 2022)

A 10.33 μJ/encryption Homomorphic Encryption Engine in 28nm CMOS with 4096-degree 109-bit Polynomials for Resource-Constrained IoT Clients. - Siddharth Das; McKenzie van der Hagen; Swarali Patil; Cagri Erbagci; Brandon Lucia; Ken Mai (ESSCIRC, 2023)

MANIC: A $19 mu mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS. - Graham Gobieski; Oguz Atli; Cagri Erbagci; Ken Mai; Nathan Beckmann; Brandon Lucia (ISCAS, 2023)

An IP-Agnostic Foundational Cell Array Offering Supply Chain Security. - Christopher Talbot; Deepali Garg; Lawrence T. Pileggi; Kenneth Mai (DAC, 2024)

A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm. - Larry Tang 003; Siyuan Chen; Keshav Harisrikanth; Guanglin Xu; Franz Franchetti; Ken Mai (HCS, 2024)

A 748 GOPS/W RISC-V SoC with Reconfigurable Custom Instructions via a Synthesized eFPGA with 1.8µs Configuration Time in 22nm FinFET. - Prashanth Mohan; Siddharth Das; Ken Mai (CICC, 2025)

A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process. - Prashanth Mohan; Siddharth Das; Oguz Atli; Josh Joffrion; Ken Mai (DATE, 2025)