A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology. - Masakazu Kurisu; Makoto Kaneko; Tetsuyuki Suzaki; Akira Tanabe; Mitsuhiro Togo; Akio Furukawa; Takao Tamura; Ken Nakajima; Kazuyoshi Yoshida (IEEE J. Solid State Circuits, 1996)

A 0.25-μm CMOS 0.9-V 100-MHz DSP core. - Masanori Izumikawa; Hiroyuki Igura; Hitoshi Wakabayashi; Ken Nakajima; Tohru Mogami; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1997)

Autonomous precision orbit control of ALOS-2 for repeat-pass SAR interferometry. - Toru Yamamoto; Isao Kawano; Takanori Iwata; Yoshihisa Arikawa; Hiroyuki Itoh; Masayuki Yamamoto; Ken Nakajima (IGARSS, 2013)

Metallic glass nanofibers in future hydrogel-based scaffolds. - Ramin Banan-Sadeghian; Samad Ahadian; Shin Yaginuma; Javier Ramón-Azcón; Xiaobin Liang; Ken Nakajima; Hitoshi Shiku; Tomokazu Matsue; Koji S. Nakayama; Ali Khademhosseini (EMBC, 2014)

Mechanism for Multithreaded and Asynchronous System Call Execution. - Ken Nakajima; Masahito Shiba (LifeTech, 2021)