Neuro-aided guidance system for optimum desulphurization treatment in torpedo cars. - Ken Nakamura; Kaichi Sagara (ICNN, 1995)

Interactive Support for Decision Making. - Noriyuki Matsuda; Ken Nakamura (HCI (2), 1997)

Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System. - Ken Nakamura; Mitsuo Ikeda; Takeshi Yoshitome; Takeshi Ogura (ITCC, 2000)

A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. - Hiroe Iwasaki; Jiro Naganuma; Yasuyuki Nakajima; Yutaka Tashiro; Ken Nakamura; Takeshi Yoshitome; Takayuki Onishi; Mitsuo Ikeda; Takaaki Izuoka; Makoto Endo (CICC, 2003)

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. - Hiroe Iwasaki; Jiro Naganuma; Koyo Nitta; Ken Nakamura; Takeshi Yoshitome; Mitsuo Ogura; Yasuyuki Nakajima; Yutaka Tashiro; Takayuki Onishi; Mitsuo Ikeda; Makoto Endo (DATE, 2003)

Scalable architecture for use in an over-HDTV real-time codec system for multiresolution video. - Takeshi Yoshitome; Ken Nakamura; Yoshiyuki Yashima; Makoto Endo (VCIP, 2003)

Super high resolution video codec system with multiple MPEG-s HDTV codec LSI's. - Ken Nakamura; Takeshi Yoshitome; Yoshiyuki Yashima (ISCAS (3), 2004)

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. - Hiroe Iwasaki; Jiro Naganuma; Koyo Nitta; Ken Nakamura; Takeshi Yoshitome; Mitsuo Ogura; Yasuyuki Nakajima; Yutaka Tashiro; Takayuki Onishi; Mitsuo Ikeda; Toshihiro Minami; Makoto Endo; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV. - Takayuki Onishi; Ken Nakamura; Takeshi Yoshitome; Jiro Naganuma (IEICE Trans. Inf. Syst., 2008)

A Flexible Video CODEC System for Super High Resolution Video. - Takeshi Yoshitome; Ken Nakamura; Jiro Naganuma; Yoshiyuki Yashima (IEICE Trans. Inf. Syst., 2008)

An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. - Koyo Nitta; Hiroe Iwasaki; Takayuki Onishi; Takashi Sano 001; Atsushi Sagata; Yasuyuki Nakajima; Minoru Inamori; Ryuichi Tanida; Atsushi Shimizu; Ken Nakamura; Mitsuo Ikeda; Jiro Naganuma (IEICE Trans. Electron., 2012)

Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. - Hiroe Iwasaki; Takayuki Onishi; Ken Nakamura; Koyo Nitta; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Jia Su; Naoki Ono; Ritsu Kusaba; Atsushi Sagata; Mitsuo Ikeda; et al. (Hot Chips Symposium, 2015)

Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. - Takayuki Onishi; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Jia Su; Ken Nakamura; Koyo Nitta; Kimiko Kawashima; Jun Okamoto; Naoki Ono; Ritsu Kusaba; Atsushi Sagata; et al. (VLSIC, 2015)

An HEVC real-time encoding system with high quality HDR color representations. - Daisuke Kobayashi; Ken Nakamura; Takayuki Onishi; Yasuyuki Nakajima; Hiroe Iwasaki; Mitsuo Ikeda; Atsushi Shimizu (ICCE, 2018)

A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations. - Daisuke Kobayashi; Ken Nakamura; Takayuki Onishi; Hiroe Iwasaki; Atsushi Shimizu (IEEE Trans. Consumer Electron., 2018)

A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. - Takayuki Onishi; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Ken Nakamura; Koyo Nitta; Kimiko Kawashima; Jun Okamoto; Naoki Ono; Atsushi Sagata; Hiroe Iwasaki; Mitsuo Ikeda; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Tatsuya Osawa; Takayuki Onishi; Koyo Nitta; Hiroe Iwasaki; Atsushi Shimizu (COOL CHIPS, 2019)

A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control. - Daisuke Kobayashi; Ken Nakamura; Tatsuya Osawa; Yuya Omori; Takayuki Onishi; Hiroe Iwasaki (GLOBECOM, 2019)

4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay. - Yuya Omori; Ken Nakamura; Takayuki Onishi; Daisuke Kobayashi; Tatsuya Osawa; Hiroe Iwasaki (ICECS, 2019)

An MMT Module for 4K/120fps Temporally Scalable Video. - Yasuhiro Mochida; Takayuki Nakachi; Takahiro Yamaguchi; Takayuki Onishi; Ken Nakamura (ISCAS, 2019)

A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. - Takayuki Onishi; Yuya Omori; Ken Nakamura; Hiroe Iwasaki; Atsushi Shimizu (ISCAS, 2019)

MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture. - Yasuhiro Mochida; Takahiro Yamaguchi; Ken Nakamura (COOL CHIPS, 2020)

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. - Ken Nakamura; Daisuke Kobayashi; Yuya Omori; Tatsuya Osawa; Takayuki Onishi; Koyo Nitta; Hiroe Iwasaki (IEICE Trans. Electron., 2020)

High-definition object detection technology based on AI inference scheme and its implementation. - Hiroyuki Uzawa; Shuhei Yoshida; Yuukou Iinuma; Saki Hatta; Daisuke Kobayashi; Yuya Omori; Ken Nakamura; Shuichi Takada; Hassan Toorabally; Kimikazu Sano (IEICE Electron. Express, 2021)

4K 120fps HEVC Encoder with Multi-Chip Configuration. - Yuya Omori; Ken Nakamura; Takayuki Onishi; Daisuke Kobayashi; Tatsuya Osawa; Hiroe Iwasaki (IEICE Trans. Commun., 2021)

An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Koyo Nitta; Kimikazu Sano; Masayuki Sato 001; Hiroe Iwasaki; Hiroaki Kobayashi (COOL CHIPS, 2022)

OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Hiroe Iwasaki; Daisuke Kobayashi; Yuya Omori; Ken Nakamura; Koyo Nitta; Kimikazu Sano (MWSCAS, 2022)

A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. - Masayuki Sato 001; Yuya Omori; Ryusuke Egawa; Ken Nakamura; Daisuke Kobayashi; Hiroe Iwasaki; Kazuhiko Komatsu; Hiroaki Kobayashi (PDCAT, 2022)

High-definition technology of AI inference scheme for object detection on edge/terminal. - Hiroyuki Uzawa; Shuhei Yoshida; Yukou Iinuma; Saki Hatta; Daisuke Kobayashi; Yuya Omori; Yusuke Horishita; Ken Nakamura; Shuichi Takada; Hassan Toorabally; Koyo Nitta; Koji Yamazaki; et al. (IEICE Electron. Express, 2023)

A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming. - Daisuke Kobayashi; Ken Nakamura; Masaki Kitahara; Tatsuya Osawa; Yuya Omori; Takayuki Onishi; Hiroe Iwasaki (IEICE Trans. Inf. Syst., 2023)

An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Koyo Nitta; Kimikazu Sano; Masayuki Sato 001; Hiroe Iwasaki; Hiroaki Kobayashi (IEICE Trans. Electron., 2023)

Decoding Algorithm Correcting Single-Insertion Plus Single-Deletion for Non-binary Quantum Codes. - Ken Nakamura; Takayuki Nozaki (ISITA, 2024)

Resource Allocation Considering the Impact of Characteristics and Parallel Processing of Heterogeneous Computational Resources in Disaggregated Computing. - Narunori Ebara; Saki Hatta; Yuta Ukon; Hiroyuki Uzawa; Shoko Ohteru; Shuhei Yoshida; Ken Nakamura (COMPSAC, 2025)

Video Transfer Method Suitable for Object Detection in the Cloud. - Mamoru Shirahase; Koyo Nitta; Yusuke Horishita; Yuya Omori; Daisuke Kobayashi; Ken Nakamura (ICCE, 2025)

Multiple-Insertion-Correcting Non-Binary Quantum Codes and Decoding Algorithm. - Ken Nakamura; Takayuki Nozaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

Correspondence of high-dimensional emotion structures elicited by video clips between humans and Multimodal LLMs. - Haruka Asanuma; Naoko Koide-Majima; Ken Nakamura; Takato Horii; Shinji Nishimoto; Masafumi Oizumi (CoRR, 2025)