Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. - Sanae Seike; Ken Namura; Yukio Ohya; Anis Uzzaman; Shinichi Arima; Dale Meehl; Vivek Chickermane; Azumi Kobayashi; Satoshi Tanaka; Hiroyuki Adachi (ATS, 2006)

A Highly Efficient Layout-Aware FPGA Overlay Accelerator Mapping Method. - Tanvir Ahmed; Johannes Maximilian Kühn; Ken Namura (MCSoC, 2021)

MN-Core - A Highly Efficient and Scalable Approach to Deep Learning. - Ken Namura; Johannes Maximilian Kühn; Tohru Adachi; H. Imachi; H. Kaneko; T. Kato; Go Watanabe; Naoto Tanaka; S. Kashihara; Hiroshi Miyashita; Y. Tomonaga; Ryosuke Okuta; et al. (VLSI Circuits, 2021)

Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units. - Toru Koizumi 001; Ryota Shioya; Takuya Yamauchi; Tomoya Adachi; Ken Namura; Jun Makino (ARITH, 2025)