A three dimensional register file for superscalar processors. - Marc Tremblay; Bill Joy 001; Ken Shin (HICSS (1), 1995)

A 64-b microprocessor with multimedia support. - Lavi Lev; Andy Charnas; Marc Tremblay; Alexander Dalal; Bruce A. Frederick; Chakra R. Srivatsa; David Greenhill; Dennis L. Wendell; Duy Dinh Pham; Eric Anderson; Hemraj K. Hingarh; Inayat Razzack; et al. (IEEE J. Solid State Circuits, 1995)

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. - Raymond A. Heald; Ken Shin; Vinita Reddy; I-Feng Kao; Masood Khan; William L. Lynch; Gary Lauterbach; Joe Petolino (IEEE J. Solid State Circuits, 1998)

A third-generation SPARC V9 64-b microprocessor. - Raymond A. Heald; Kathirgamar Aingaran; Chaim Amir; Michael Ang; Michael Boland; Pankaj Dixit; Gary Gouldsberry; Dale Greenley; Joel Grinberg; Jason M. Hart; Tim Horel; Wen-Jay Hsu; et al. (IEEE J. Solid State Circuits, 2000)

Scan-controlled pulse flip-flops for mobile application processors. - Min-Su Kim; Hyoungwook Lee; Jin-Soo Park; Chunghee Kim; Juhyun Kang; Ken Shin; Emil Kagramanyan; Gunok Jung; Ukrae Cho; Youngmin Shin; Jae-Cheol Son (ISCAS, 2013)

28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor. - Youngmin Shin; Ken Shin; Prashant Kenkare; Rajesh Kashyap; Hoi-Jin Lee; Dongjoo Seo; Brian Millar; Yohan Kwon; Ravi Iyengar; Min-Su Kim; Ahsan Chowdhury; Sung-il Bae; et al. (ISSCC, 2013)

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor. - Jungyul Pyo; Youngmin Shin; Hoi-Jin Lee; Sung-il Bae; Min-Su Kim; Kwangil Kim; Ken Shin; Yohan Kwon; Heungchul Oh; Jaeyoung Lim; Dong-Wook Lee; Jongho Lee; et al. (ISSCC, 2015)