Design Considerations for an Information Query Computer. - Akira Sekino; Ken Takeuchi; Takenori Makino; Katsuya Hakozaki; Tsugunori Doi; Tatsuo Goto (Advanced Database Machine Architecture, 1983)

Relational Data Base Systems INQ and RIOS. - Kazuyuki Hara; Tatsuo Gotoh; Tsuyoshi Miyazaki 001; Ken Takeuchi; Shigeru Mabuchi (IEEE Database Eng. Bull., 1983)

A double-level-Vth select gate array architecture for multilevel NAND flash memories. - Ken Takeuchi; Tomoharu Tanaka; Hiroshi Nakamura (IEEE J. Solid State Circuits, 1996)

A compact on-chip ECC for low cost flash memories. - Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Riichiro Shirota; Seiichi Aritome; Hiroshi Watanabe; Gertjan Hemink; Kazuhiro Shimizu; Shinji Sato; Yuji Takeuchi; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1997)

A multipage cell architecture for high-speed programming multilevel NAND flash memories. - Ken Takeuchi; Tomoharu Tanaka; Toru Tanzawa (IEEE J. Solid State Circuits, 1998)

A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. - Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Toshihiko Himeno; Ken Takeuchi; Tamio Ikehashi; Kazushige Kanda; Koji Hosono; Riichiro Shirota; Seiichi Aritome; Kazuhiro Shimizu; Kazuo Hatakeyama; et al. (IEEE J. Solid State Circuits, 1999)

A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. - Ken Takeuchi; Shinji Satoh; Tomoharu Tanaka; Ken-ichi Imamiya; Koji Sakui (IEEE J. Solid State Circuits, 1999)

A source-line programming scheme for low-voltage operation NAND flash memories. - Ken Takeuchi; Shinji Satoh; Ken-ichi Imamiya; Koji Sakui (IEEE J. Solid State Circuits, 2000)

A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories. - Ken Takeuchi; Tomoharu Tanaka (IEEE J. Solid State Circuits, 2001)

A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. - Kenichi Imamiya; Hiroshi Nakamura; Toshihiko Himeno; Toshio Yamamura; Tamio Ikehashi; Ken Takeuchi; Kazushige Kanda; Koji Hosono; Takuya Futatsuyama; Koichi Kawai; Riichiro Shirota; Norihisa Arai; et al. (IEEE J. Solid State Circuits, 2002)

Circuit techniques for a 1.8-V-only NAND flash memory. - Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Hiroshi Nakamura (IEEE J. Solid State Circuits, 2002)

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (ISSCC, 2006)

A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. - Ken Takeuchi; Yasushi Kameda; Susumu Fujimura; Hiroyuki Otake; Koji Hosono; Hitoshi Shiga; Yoshihisa Watanabe; Takuya Futatsuyama; Yoshihiko Shindo; Masatsugu Kojima; Makoto Iwai; Masanobu Shirakawa; et al. (IEEE J. Solid State Circuits, 2007)

Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (3DIC, 2009)

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (ISLPED, 2009)

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. - Koichi Ishida; Tadashi Yasufuku; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (ISSCC, 2009)

SSD memory subsystem innovation. - Ken Takeuchi (ISSCC, 2009)

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD). - Ken Takeuchi (IEEE J. Solid State Circuits, 2009)

Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. - Kentaro Honda; Kousuke Miyaji; Shuhei Tanakamaru; Shinji Miyano; Ken Takeuchi (CICC, 2010)

Silicon 3D-integration technology and systems. - Pascal Urard; Ken Takeuchi; Kerry Bernstein; Hideto Hidaka; Michael Phan; Joo-Sun Choi; Bob Payne; Vladimir Stojanovic; Kees van Berkel 001; Takayasu Sakurai (ISSCC, 2010)

Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (IEICE Trans. Electron., 2010)

Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives. - Teruyoshi Hatanaka; Ryoji Yajima; Takeshi Horiuchi; Shouyu Wang; Xizhen Zhang; Mitsue Takahashi; Shigeki Sakai; Ken Takeuchi (IEEE J. Solid State Circuits, 2010)

A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives. - Teruyoshi Hatanaka; Koh Johguchi; Ken Takeuchi (3DIC, 2011)

Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM. - Kousuke Miyaji; Yasuhiro Shinozuka; Shinji Miyano; Ken Takeuchi (CICC, 2011)

Green high performance storage class memory & NAND flash memory hybrid SSD system. - Ken Takeuchi (ISLPED, 2011)

Ultra-low voltage VLSIs for energy efficient systems. - Ken Takeuchi; Ken Chang; Kevin Zhang; Tadaaki Yamauchi; Roberto Gastaldi (ISSCC, 2011)

95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. - Shuhei Tanakamaru; Chinglin Hung; Atsushi Esumi; Mitsuyoshi Ito; Kai Li; Ken Takeuchi (ISSCC, 2011)

Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs). - Teruyoshi Hatanaka; Mitsue Takahashi; Shigeki Sakai; Ken Takeuchi (IEICE Trans. Electron., 2011)

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. - Koichi Ishida; Tadashi Yasufuku; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (IEEE J. Solid State Circuits, 2011)

Improvement of Read Margin and Its Distribution by VTH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. - Kousuke Miyaji; Shuhei Tanakamaru; Kentaro Honda; Shinji Miyano; Ken Takeuchi (IEEE J. Solid State Circuits, 2011)

A 0.5 V Operation V TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems. - Shuhei Tanakamaru; Ken Takeuchi (IEEE J. Solid State Circuits, 2011)

A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. - Kousuke Miyaji; Toshikazu Suzuki; Shinji Miyano; Ken Takeuchi (ISSCC, 2012)

Robust VLSI circuit design & systems for sustainable society. - Ken Takeuchi; Jan Crols; Kevin Zhang; Mike Clinton; Tadaaki Yamauchi (ISSCC, 2012)

Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. - Shuhei Tanakamaru; Yuki Yanagihara; Ken Takeuchi (ISSCC, 2012)

x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression. - Hiroki Fujii; Kousuke Miyaji; Koh Johguchi; Kazuhide Higuchi; Chao Sun 001; Ken Takeuchi (VLSIC, 2012)

Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs). - Ken Takeuchi; Teruyoshi Hatanaka; Shuhei Tanakamaru (IEICE Electron. Express, 2012)

Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor. - Kousuke Miyaji; Kentaro Honda; Shuhei Tanakamaru; Shinji Miyano; Ken Takeuchi (IEICE Trans. Electron., 2012)

Initialize and Weak-Program Erasing Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive. - Kousuke Miyaji; Ryoji Yajima; Teruyoshi Hatanaka; Mitsue Takahashi; Shigeki Sakai; Ken Takeuchi (IEICE Trans. Electron., 2012)

NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD. - Teruyoshi Hatanaka; Ken Takeuchi (IEEE J. Solid State Circuits, 2012)

Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. - Shuhei Tanakamaru; Chinglin Hung; Ken Takeuchi (IEEE J. Solid State Circuits, 2012)

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. - Alice Wang; Ken Takeuchi; Tanay Karnik; Maysam Ghovanloo; Satoshi Shigematsu (IEEE J. Solid State Circuits, 2012)

Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM. - Kousuke Miyaji; Yasuhiro Shinozuka; Shinji Miyano; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression. - Chao Sun 001; Hiroki Fujii; Kousuke Miyaji; Koh Johguchi; Kazuhide Higuchi; Ken Takeuchi (ASP-DAC, 2013)

Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. - Shuhei Tanakamaru; Yuki Yanagihara; Ken Takeuchi (ASP-DAC, 2013)

Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory. - Ken Takeuchi (CICC, 2013)

Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (ISSCC, 2013)

A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. - Kousuke Miyaji; Toshikazu Suzuki; Shinji Miyano; Ken Takeuchi (IEEE J. Solid State Circuits, 2013)

Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). - Shuhei Tanakamaru; Yuki Yanagihara; Ken Takeuchi (IEEE J. Solid State Circuits, 2013)

Hybrid solid-state storage system with storage class memory and NAND flash memory for big-data application. - Ken Takeuchi (ISCAS, 2014)

A workload-aware-design of 3D-NAND flash memory for enterprise SSDs. - Chao Sun 001; Ayumi Soga; Takahiro Onagi; Koh Johguchi; Ken Takeuchi (ISQED, 2014)

19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. - Shuhei Tanakamaru; Hiroki Yamazawa; Tsukasa Tokutomi; Sheyang Ning; Ken Takeuchi (ISSCC, 2014)

Application-aware solid-state drives (SSDs) with adaptive coding. - Shuhei Tanakamaru; Yuta Kitamura; Senju Yamazaki; Tsukasa Tokutomi; Ken Takeuchi (VLSIC, 2014)

A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories. - Koh Johguchi; Toru Egami; Kousuke Miyaji; Ken Takeuchi (IEICE Trans. Electron., 2014)

NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance. - Koh Johguchi; Kasuaki Yoshioka; Ken Takeuchi (IEICE Trans. Electron., 2014)

Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD. - Chao Sun 001; Tomoko Ogura Iwasaki; Takahiro Onagi; Koh Johguchi; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD. - Chao Sun 001; Kousuke Miyaji; Koh Johguchi; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory. - Shogo Hachiya; Takahiro Onagi; Sheyang Ning; Ken Takeuchi (3DIC, 2015)

0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications. - Tomoya Ishii; Shogo Hachiya; Sheyang Ning; Masahiro Tanaka; Ken Takeuchi (A-SSCC, 2015)

7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. - Tsukasa Tokutomi; Masafumi Doi; Shogo Hachiya; Atsuro Kobayashi; Shuhei Tanakamaru; Ken Takeuchi (ISSCC, 2015)

Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (VLSIC, 2015)

Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten. - Shuhei Tanakamaru; Hiroki Yamazawa; Ken Takeuchi (VLSIC, 2015)

Reliability enhancement of 1Xnm TLC for cold flash and millennium memories. - Senju Yamazaki; Shuhei Tanakamaru; Sakuya Suzuki; Tomoko Ogura Iwasaki; Shogo Hachiya; Ken Takeuchi (VLSIC, 2015)

A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. - Shuhei Tanakamaru; Masafumi Doi; Ken Takeuchi (IEICE Trans. Electron., 2015)

SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform. - Chao Sun 001; Asuka Arakawa; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). - Shuhei Tanakamaru; Yuta Kitamura; Senju Yamazaki; Tsukasa Tokutomi; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. - Shuhei Tanakamaru; Hiroki Yamazawa; Tsukasa Tokutomi; Sheyang Ning; Ken Takeuchi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

System-Level Considerations on Design of 3D NAND Flash Memories. - Chao Sun 001; Ken Takeuchi (3D Flash Memories, 2016)

Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process. - Masahiro Tanaka; Kota Tsurumi; Tomoya Ishii; Ken Takeuchi (ESSCIRC, 2016)

Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers. - Atsuro Kobayashi; Tsukasa Tokutomi; Ken Takeuchi (VLSI Circuits, 2016)

Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths. - Hirofumi Takishita; Shuhei Tanakamaru; Sheyang Ning; Ken Takeuchi (IEICE Trans. Electron., 2016)

Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications. - Tomoya Ishii; Sheyang Ning; Masahiro Tanaka; Kota Tsurumi; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. - Sheyang Ning; Tomoko Ogura Iwasaki; Shuhei Tanakamaru; Darlene Viviani; Henry Huang; Monte Manning; Thomas Rueckes; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

Design guidelines of storage class memory/flash hybrid solid-state drive considering system architecture, algorithm and workload characteristic. - Chao Sun 001; Shun Okamoto; Shogo Hachiya; Tomoaki Yamada; Ken Takeuchi (IEEE Trans. Consumer Electron., 2016)

LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives. - Chao Sun 001; Ayumi Soga; Chihiro Matsui; Asuka Arakawa; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. - Shuhei Tanakamaru; Shogo Hosaka; Koh Johguchi; Hirofumi Takishita; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data. - Yoshiaki Deguchi; Ken Takeuchi (A-SSCC, 2017)

MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage. - Hikaru Watanabe; Yoshiaki Deguchi; Ken Takeuchi (A-SSCC, 2017)

12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. - Yoshiaki Deguchi; Toshiki Nakamura; Atsuro Kobayashi; Ken Takeuchi (CICC, 2017)

Study of error repeatability and recovery in 40nm TaOx ReRAM. - Takashi Inose; Seiichi Aritome; Ryutaro Yasuhara; Satoshi Mishima; Ken Takeuchi (ESSDERC, 2017)

22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash. - Chihiro Matsui; Ken Takeuchi (ESSDERC, 2017)

0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives. - Kota Tsurumi; Masahiro Tanaka; Ken Takeuchi (ISQED, 2017)

Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs. - Tomoaki Yamada; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2017)

Image Retrieval Method for Multiscale Objects from Optical Colonoscopy Images. - Hirokazu Nosato; Hidenori Sakanashi; Eiichi Takahashi; Masahiro Murakawa; Hiroshi Aoki; Ken Takeuchi; Yasuo Suzuki (Int. J. Biomed. Imaging, 2017)

Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory. - Chihiro Matsui; Chao Sun 001; Ken Takeuchi (Proc. IEEE, 2017)

Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD. - Chihiro Matsui; Asuka Arakawa; Chao Sun 001; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD. - Kota Tsurumi; Kenta Suzuki; Ken Takeuchi (A-SSCC, 2018)

9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories. - Toshiki Nakamura; Yoshiaki Deguchi; Ken Takeuchi (CICC, 2018)

Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAM. - Kazuki Maeda; Shinpei Matsuda; Ken Takeuchi; Ryutaro Yasuhara (ESSDERC, 2018)

Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x. - Shun Suzuki; Yoshiaki Deguchi; Toshiki Nakamura; Ken Takeuchi (ESSDERC, 2018)

Suppression of endurance-stressed data-retention failures of 40nm TaOx-based ReRAM. - Shouhei Fukuyama; Kazuki Maeda; Shinpei Matsuda; Ken Takeuchi; Ryutaro Yasuhara (IRPS, 2018)

Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs. - Shun Suzuki; Yoshiaki Deguchi; Toshiki Nakamura; Kyoji Mizoguchi; Ken Takeuchi (IRPS, 2018)

20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD. - Mamoru Fukuchi; Yukiya Sakaki; Chihiro Matsui; Ken Takeuchi (ISCAS, 2018)

Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network. - Atsuna Hayakawa; Toshiki Nakamura; Yoshiaki Deguchi; Kazuki Maeda; Ken Takeuchi (ISCAS, 2018)

3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage. - Chihiro Matsui; Ken Takeuchi (ISCAS, 2018)

Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition. - Keita Mizushina; Toshiki Nakamura; Yoshiaki Deguchi; Ken Takeuchi (ISCAS, 2018)

Improvement of Endurance and Data-retention in 40nm TaOX-based ReRAM by Finalize Verify. - Shouhei Fukuyama; Shinpei Matsuda; Ryutaro Yasuhara; Ken Takeuchi (NVMTS, 2018)

Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM. - Reika Kinoshita; Chihiro Matsui; Shinpei Matsuda; Yutaka Adachi; Ken Takeuchi (NVMTS, 2018)

Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature. - Atsuya Suzuki; Chihiro Matsui; Ken Takeuchi (NVMTS, 2018)

Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs. - Yutaka Adachi; Chihiro Matsui; Ken Takeuchi (VLSI-DAT, 2018)

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. - Kuniyuki Kakushima; Takuya Hoshii; M. Watanabe; N. Shizyo; K. Furukawa; Takuya Saraya; T. Takakura; K. Itou; M. Fukui; S. Suzuki; Ken Takeuchi; Iriya Muneta; et al. (VLSI Circuits, 2018)

Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size. - Hirofumi Takishita; Yutaka Adachi; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2018)

Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test. - Yusuke Yamaga; Chihiro Matsui; Yukiya Sakaki; Ken Takeuchi (IEICE Trans. Electron., 2018)

Write and Read Frequency-Based Word-Line Batch VTH Modulation for 2-D and 3-D-TLC NAND Flash Memories. - Yoshiaki Deguchi; Shun Suzuki; Ken Takeuchi (IEEE J. Solid State Circuits, 2018)

Switching of 3300V Scaled IGBT by 5V Gate Drive. - Toshiro Hiramoto; Katsumi Satoh; Tomoko Matsudai; Wataru Saito; Kuniyuki Kakushima; Takuya Hoshii; Kazuyoshi Furukawa; Masahiro Watanabe; Naoyuki Shigyo; Hitoshi Wakabayashi; Kazuo Tsutsui; Hiroshi Iwai; et al. (ASICON, 2019)

Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories. - Chihiro Matsui; Ken Takeuchi (ASP-DAC, 2019)

Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing. - Shun Suzuki; Kyoji Mizoguchi; Hikaru Watanabe; Toshiki Nakamura; Yoshiaki Deguchi; Keita Mizushina; Ken Takeuchi (A-SSCC, 2019)

Parallel Product-Sum Operation Neuromorphic Systems with 4-bit Ferroelectric FET Synapses. - Koki Kamimura; Susumu Nohmi; Kenta Suzuki; Ken Takeuchi (ESSDERC, 2019)

Comprehensive Analysis of Data-Retention and Endurance Trade-Off of 40nm TaOx-based ReRAM. - Shouhei Fukuyama; Atsuna Hayakawa; Ryutaro Yasuhara; Shinpei Matsuda; Hiroshi Kinoshita; Ken Takeuchi (IRPS, 2019)

Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime Extension. - Kyoji Mizoguchi; Kyosuke Maeda; Ken Takeuchi (IRPS, 2019)

Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories. - Chihiro Matsui; Ken Takeuchi (ISCAS, 2019)

Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. - Chihiro Matsui; Ken Takeuchi (Integr., 2019)

Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits. - Ken Chang; Ken Takeuchi (IEEE J. Solid State Circuits, 2019)

3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition. - Yoshiaki Deguchi; Toshiki Nakamura; Atsuna Hayakawa; Ken Takeuchi (IEEE J. Solid State Circuits, 2019)

Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories. - Toshiki Nakamura; Yoshiaki Deguchi; Ken Takeuchi (IEEE J. Solid State Circuits, 2019)

Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory. - Chihiro Matsui; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance. - Reika Kinoshita; Chihiro Matsui; Atsuya Suzuki; Shouhei Fukuyama; Ken Takeuchi (ASP-DAC, 2020)

Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers. - Yoshiki Kakuta; Reika Kinoshita; Hiroshi Kinoshita; Chihiro Matsui; Ken Takeuchi (VLSI-DAT, 2020)

System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs. - Mamoru Fukuchi; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2020)

Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs). - Yoshiki Takai; Mamoru Fukuchi; Chihiro Matsui; Reika Kinoshita; Ken Takeuchi (IEICE Trans. Electron., 2020)

Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing. - Shun Suzuki; Hiroki Aihara; Ken Takeuchi (IEEE J. Solid State Circuits, 2020)

Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits. - Ken Takeuchi; Brian P. Ginsburg (IEEE J. Solid State Circuits, 2020)

Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory. - Kenta Taoka; Naoko Misawa; Shunsuke Koshino; Chihiro Matsui; Ken Takeuchi (IMW, 2021)

BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads. - Mamoru Fukuchi; Shun Suzuki; Kyosuke Maeda; Chihiro Matsui; Ken Takeuchi (ISCAS, 2021)

Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory. - Daiki Kojima; Ken Takeuchi (ISCAS, 2021)

SE1: What Technologies Will Shape the Future of Computing? - Hugh Mair; Shinichiro Shiratake; Eric Karl; Thomas Burd; Jonathan Chang; Debbie Marr; Samuel Naffziger; Henk Corporaal; Ken Takeuchi; Naresh R. Shanbhag (ISSCC, 2021)

Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing. - Chihiro Matsui; Kasidit Toprasertpong; Shinichi Takagi; Ken Takeuchi (VLSI Circuits, 2021)

Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM. - Yuya Ichikawa; Akira Goda; Chihiro Matsui; Ken Takeuchi (IMW, 2022)

Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation. - Shinsei Yoshikiyo; Naoko Misawa; Kasidit Toprasertpong; Shinichi Takagi; Chihiro Matsui; Ken Takeuchi (IMW, 2022)

Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing. - Chihiro Matsui; Eitaro Kobayashi; Kasidit Toprasertpong; Shinichi Takagi; Ken Takeuchi (ISCAS, 2022)

Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing. - Naoko Misawa; Kenta Taoka; Chihiro Matsui; Ken Takeuchi (ISCAS, 2022)

Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation. - Shinsei Yoshikiyo; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (ISCAS, 2022)

Foreword. - Ken Takeuchi (A-SSCC, 2023)

LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory. - Ayumu Yamada; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (ICCAD, 2023)

Analog Computation-in-Memory (CiM) for AI Applications. - Ken Takeuchi (ICICDT, 2023)

Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance. - Takuto Nishimura; Yuya Ichikawa; Akira Goda; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IMW, 2023)

Neuromorphic Computation-in-Memory System (Invited). - Ken Takeuchi (IRPS, 2023)

ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset. - Ayumu Yamada; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IRPS, 2023)

Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads. - Chihiro Matsui; Ken Takeuchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM. - Shinsei Yoshikiyo; Naoko Misawa; Kasidit Toprasertpong; Shinichi Takagi; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2023)

Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers. - Naoko Misawa; Tao Wang; Chihiro Matsui; Ken Takeuchi (IMW, 2024)

REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night. - Yuya Ichikawa; Ayumu Yamada; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2024)

3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing. - Fuyuki Kihara; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2024)

Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern Classifier. - Ayumu Yamada; Zhiyuan Huang; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Electron., 2024)

FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. - Chihiro Matsui; Kasidit Toprasertpong; Shinichi Takagi; Ken Takeuchi (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC). - Ken Takeuchi; Tetsuya Iizuka; Kazuko Nishimura; Jerald Yoo (IEEE J. Solid State Circuits, 2024)

Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices. - Naoko Misawa; Tao Wang 126; Chihiro Matsui; Ken Takeuchi (ASP-DAC, 2025)

Hybrid ReRAM-NMC & SRAM-CiM Matrix Multiplication for Large Language Model. - Tao Wang; Daqi Lin; Kenshin Yamauchi; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (COOL CHIPS, 2025)

Bayesian Neural Network Realization by Random Telegraph Noise in 40nm TaOX ReRAM CiM. - Junnosuke Furukawa; Koki Shibata; Kenshin Yamauchi; Naoko Misawa; Satoshi Awamura; Chihiro Matsui; Ken Takeuchi (IMW, 2025)

Conductance Variation-Assisted Adversarial Attack Robustness on 40nm TaOx-based ReRAM CiM. - Kenshin Yamauchi; Naoko Misawa; Satoshi Awamura; Masahiro Morimoto; Chihiro Matsui; Ken Takeuchi (IRPS, 2025)

Read Voltage Dependency of Random Telegraph Noise in the Intermediate State of TaOx-based ReRAM. - Kenshin Yamauchi; Naoko Misawa; Hisashi Shima; Yasuhisa Naitoh; Hiroyuki Akinaga; Chihiro Matsui; Ken Takeuchi (IRPS, 2025)

VaLI: Variability-aware Fine-tuning with Low-rank Adapter and Iterative Training for ReRAM Computation-in-Memory. - Tao Wang; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (ISCAS, 2025)

RGB-Event Multi-Modal NV-CiM to Detect Object by Mapping-Oriented Enhanced-Feature Pyramid Network with Mapping-Aware Group Convolution. - Yuya Ichikawa; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation. - Fuyuki Kihara; Seiji Uenohara; Satoshi Awamura; Naoko Misawa; Chihiro Matsui; Ken Takeuchi (CoRR, 2025)