A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS. - Hirotomo Ishii; Ken Tanabe; Tetsuya Iida (CICC, 2005)

A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC. - Pedro M. Figueiredo; Paulo Cardoso; Ana Lopes; Carlos Fachada; Naoyuki Hamanishi; Ken Tanabe; João C. Vital (ISSCC, 2006)

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (CICC, 2009)

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. - Tetsuro Matsuno; Daisuke Fujimoto; Daisuke Kosaka; Naoyuki Hamanishi; Ken Tanabe; Masazumi Shiochi; Makoto Nagata (IEICE Trans. Electron., 2010)

Provably Safe and Robust Drone Routing via Sequential Path Planning: A Case Study in San Francisco and the Bay Area. - Mo Chen 001; Somil Bansal; Ken Tanabe; Claire J. Tomlin (CoRR, 2017)

Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR. - Ken Tanabe; Hiroshi Kubota; Akihide Sai; Nobu Matsumoto (COOL CHIPS, 2018)

Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR. - Ken Tanabe; Hiroshi Kubota; Akihide Sai; Nobu Matsumoto (COOL CHIPS, 2019)

Provably Safe and Scalable Multivehicle Trajectory Planning. - Somil Bansal; Mo Chen 001; Ken Tanabe; Claire J. Tomlin (IEEE Trans. Control. Syst. Technol., 2021)