A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. - Kazuyuki Nakamura; Koichi Takeda 001; Hideo Toyoshima; Kenji Noda; Hiroaki Ohkubo; Tetsuya Uchida; Toshiyuki Shimizu; Toshiro Itani; Ken Tokashiki; Koji Kishimoto (IEEE J. Solid State Circuits, 1997)