The design and analysis of a DLL-based frequency synthesizer for UWB application. - Tai-Cheng Lee; Keng-Jan Hsiao (IEEE J. Solid State Circuits, 2006)

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation. - Keng-Jan Hsiao; Tai-Cheng Lee (ISSCC, 2008)

The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning. - Keng-Jan Hsiao; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2008)

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation. - Keng-Jan Hsiao; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2009)

An injection-locked ring PLL with self-aligned injection window. - Che-Fu Liang; Keng-Jan Hsiao (ISSCC, 2011)

A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation. - Keng-Jan Hsiao (VLSIC, 2012)

17.7 A 1.89nW/0.15V self-charged XO for real-time clock generation. - Keng-Jan Hsiao (ISSCC, 2014)

A 130dB PSRR, 108dB DR and 95dB SNDR, ground-referenced audio decoder with PSRR-enhanced load-adaptive Class-G 16Ohm headphone amplifiers. - Shon-Hang Wen; Chien-Ming Chen; Cheng-Chung Yang; Chieh-Hung Chen; Jia-Feng Jiang; Keng-Jan Hsiao; Cheng-Yu Chien (A-SSCC, 2015)

A Load-Adaptive Class-G Headphone Amplifier With Supply-Rejection Bandwidth Enhancement Technique. - Shon-Hang Wen; Chien-Ming Chen; Cheng-Chung Yang; Chieh-Hung Chen; Jia-Feng Jiang; Keng-Jan Hsiao; Cheng-Yu Chien (IEEE J. Solid State Circuits, 2016)