A PLL clock generator with 5 to 110 MHz of lock range for microprocessors. - Ian A. Young; Jeffrey K. Greason; Keng L. Wong (IEEE J. Solid State Circuits, 1992)

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor. - Robert F. Krick; Lawrence T. Clark; Daniel J. Deleganes; Keng L. Wong; Roshan Fernando; Goutam Debnath; Jashojiban Banik (IEEE J. Solid State Circuits, 1994)

A high performance 0.35-μm 3.3-V BiCMOS technology optimized for product porting from a 0.6-μm 3.3-V BiCMOS technology. - Jashojiban Banik; Keng L. Wong; George L. Geannopoulos; Chung Y. Joseph Yip (IEEE J. Solid State Circuits, 1996)

Enhancing microprocessor immunity to power supply noise with clock-data compensation. - Keng L. Wong; Tawfik Rahal-Arabi; Matthew Ma; Greg Taylor (IEEE J. Solid State Circuits, 2006)

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process. - David E. Duarte; George L. Geannopoulos; Usman Mughal; Keng L. Wong; Greg Taylor (CICC, 2007)

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor. - David E. Duarte; Greg Taylor; Keng L. Wong; Usman Mughal; George L. Geannopoulos (ISLPED, 2007)

Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. - David E. Duarte; Suching Hsu; Keng L. Wong; Mingwei Huang; Greg Taylor (CICC, 2010)