Very Short Critical Path Implementation of AES with Direct Logic Gates. - Kenta Nekado; Yasuyuki Nogami; Kengo Iokibe (IWSEC, 2012)

Estimation of data-dependent power voltage variations of FPGA by equivalent circuit modeling from on-board measurements. - Kengo Iokibe; Yoshitaka Toyota (EMC Compo, 2013)

Suppression of Mode Conversion by Using Tightly Coupled Asymmetrically Tapered Bend in Differential Lines. - Yoshitaka Toyota; Shohei Kan; Kengo Iokibe (IEICE Trans. Commun., 2015)

FPGA Implementation of Various Elliptic Curve Pairings over Odd Characteristic Field with Non Supersingular Curves. - Yasuyuki Nogami; Hiroto Kagotani; Kengo Iokibe; Hiroyuki Miyatake; Takashi Narita (IEICE Trans. Inf. Syst., 2016)

Connector Model for Use in Common-Mode Antenna Model Used to Estimate Radiation from Printed Circuit Boards with Board-to-Board Connector. - Yuri Wakaduki; Tetsushi Watanabe; Yoshitaka Toyota; Kengo Iokibe; Liuji R. Koga; Osami Wada (IEICE Trans. Commun., 2016)

An Approach for Attacking Speck on Microcontroller with Correlation Power Analysis. - Jianjie Tang; Kengo Iokibe; Takuya Kusaka; Yasuyuki Nogami (CANDAR (Workshops), 2020)

Mitigating differential skew by rotating meshed ground for high-density layout in flexible printed circuits. - Chenyu Wang; Kengo Iokibe; Yoshitaka Toyota (IEICE Electron. Express, 2020)

Practical Design Methodology of Mode-Conversion-Free Tightly Coupled Asymmetrically Tapered Bend for High-Density Differential Wiring. - Chenyu Wang; Kengo Iokibe; Yoshitaka Toyota (IEICE Trans. Commun., 2021)

Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices. - Yusuke Yano; Kengo Iokibe; Toshiaki Teshima; Yoshitaka Toyota; Toshihiro Katashita; Yohei Hori (IEICE Trans. Commun., 2021)

Identification of Dominant Side-Channel Information Leaking Mechanism Induced by Split Ground Planes. - Kengo Iokibe; Kohei Shimoda; Masaki Himuro; Yoshitaka Toyota (IEICE Trans. Commun., 2024)