Hybrid BIST Using Partially Rotational Scan. - Kenichi Ichino; Takeshi Asakawa; Satoshi Fukumoto; Kazuhiko Iwasaki; Seiji Kajihara (Asian Test Symposium, 2001)

Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. - Yuki Yamagata; Kenichi Ichino; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Masayuki Satoh; Hiroyuki Itabashi; Takashi Murai; Nobuyuki Otsuka (Asian Test Symposium, 2003)

Seed Selection Procedure for LFSR-Based Random Pattern Generators. - Kenichi Ichino; Ko-ichi Watanabe; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. - Masayuki Arai; Harunobu Kurokawa; Kenichi Ichino; Satoshi Fukumoto; Kazuhiko Iwasaki (Asian Test Symposium, 2004)

Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits. - Kenichi Ichino; Ko-ichi Watanabe; Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2004)

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development. - Masayuki Sato; Hiroki Wakamatsu; Masayuki Arai; Kenichi Ichino; Kazuhiko Iwasaki; Takeshi Asakawa (J. Inf. Process. Syst., 2008)