Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise. - Satoshi Imai; Atsuki Inoue; Motoaki Matsumura; Kenichi Kawasaki; Atsuhiro Suga (ASP-DAC, 2006)

A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support. - Kenichi Kawasaki; Tetsuyoshi Shiota; Koichi Nakayama; Atsuki Inoue (IEEE J. Solid State Circuits, 2009)

A Millimeter-Wave Intra-Connect Solution. - Kenichi Kawasaki; Yoshiyuki Akiyama; Kenji Komori; Masahiro Uno; Hidenori Takeuchi; Tomoari Itagaki; Yasufumi Hino; Yoshinobu Kawasaki; Katsuhisa Ito; Ali Hajimiri (IEEE J. Solid State Circuits, 2010)

A 12.5+12.5Gb/s full-duplex plastic waveguide interconnect. - Satoshi Fukuda; Yasufumi Hino; Sho Ohashi; Takahiro Takeda; Satoru Shinke; Masahiro Uno; Kenji Komori; Yoshiyuki Akiyama; Kenichi Kawasaki; Ali Hajimiri (ISSCC, 2011)

A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect. - Satoshi Fukuda; Yasufumi Hino; Sho Ohashi; Takahiro Takeda; Hiroyuki Yamagishi; Satoru Shinke; Kenji Komori; Masahiro Uno; Yoshiyuki Akiyama; Kenichi Kawasaki; Ali Hajimiri (IEEE J. Solid State Circuits, 2011)

A versatile multi-modality serial link. - Yusuke Tanaka; Yasufumi Hino; Yasuhiro Okada; Takahiro Takeda; Sho Ohashi; Hiroyuki Yamagishi; Kenichi Kawasaki; Ali Hajimiri (ISSCC, 2012)

Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology. - Kentaro Kawakami; Takeshi Shiro; Hironobu Yamasaki; Katsuhiro Yoda; Hiroaki Fujimoto; Kenichi Kawasaki; Yasuhiro Watanabe (ISQED, 2013)