A method for linking process-level variability to system performances. - Tomohiro Fujita; Ken-ichi Okada 001; Hiroaki Fujita; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 2000)

Statistical modeling of device characteristics with systematic fluctuation. - Kenichi Okada 001; Hidetoshi Onodera (ISCAS, 2000)

A statistical gate delay model for intra-chip and inter-chip variabilities. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ASP-DAC, 2003)

A Statistical Gate-Delay Model Considering Intra-Gate Variability. - Ken-ichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ICCAD, 2003)

Statistical modeling of gate-delay variation with consideration of intra-gate variability. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ISCAS (5), 2003)

Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence. - Kenichi Okada 001; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Statistical Gate-Delay Modeling with Intra-Gate Variability. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Differential transmission line interconnect for high speed and low power global wiring. - Shinichiro Gomi; Kohichi Nakamura; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (CICC, 2004)

ULSI Interconnect Length Distribution Model Considering Core Utilization. - Hidenari Nakashima; Junpei Inoue; Kenichi Okada 001; Kazuya Masu (DATE, 2004)

Modelling and optimization of on-chip spiral inductor in S-parameter domain. - Ken-ichi Okada 001; Hiroaki Hoshino; Hidetoshi Onodera (ISCAS (5), 2004)

High speed and low power on-chip micro network circuit with differential transmission line. - Shinichiro Gomi; Kohichi Nakamura; Hiroyuki Ito; Hideyuki Sugita; Kenichi Okada 001; Kazuya Masu (SoC, 2004)

Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. - Yoshiaki Yoshihara; Hirotaka Sugawara; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (IEICE Electron. Express, 2004)

Evaluation of on-chip transmission line interconnect using wire length distribution. - Junpei Inoue; Hiroyuki Ito; Shinichiro Gomi; Takanori Kyogoku; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2005)

A dynamic reconfigurable RF circuit architecture. - Kenichi Okada 001; Yoshiaki Yoshihara; Hirotaka Sugawara; Kazuya Masu (ASP-DAC, 2005)

Wire Length Distribution Model Considering Core Utilization for System on Chip. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ISVLSI, 2005)

Prediction of delay time for future LSI using on-chip transmission line interconnects. - Takumi Uezono; Junpei Inoue; Takanori Kyogoku; Kenichi Okada 001; Kazuya Masu (SLIP, 2005)

Wire Length Distribution Model for System LSI. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. - Hidenari Nakashima; Junpei Inoue; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Evaluation of X Architecture Using Interconnect Length Distribution. - Hidenari Nakashima; Naohiro Takagi; Junpei Inoue; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit. - Yoshiaki Yoshihara; Hirotaka Sugawara; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Reconfigurable CMOS low noise amplifier for self compensation. - D. Kawazoe; Hirotaka Sugawara; Tatsuya Ito; Kenichi Okada 001; Kazuya Masu (ISCAS, 2006)

Via Distribution Model for Yield Estimation. - Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ISQED, 2006)

Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. - Kenichi Okada 001; Takumi Uezono; Kazuya Masu (PATMOS, 2006)

RF Passive Components Using Metal Line on Si CMOS. - Kazuya Masu; Kenichi Okada 001; Hiroyuki Ito (IEICE Trans. Electron., 2006)

Statistical Modeling of a Via Distribution for Yield Estimation. - Takumi Uezono; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. - Satoshi Fukuda; D. Kawazoe; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2007)

A Wideband CMOS LC-VCO Using Variable Inductor. - Kazuma Ohashi; Yusaku Ito; Yoshiaki Yoshihara; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2007)

A Multi-Drop Transmission-Line Interconnect in Si LSI. - Junki Seita; Hiroyuki Ito; Kenichi Okada 001; Takashi Sato 001; Kazuya Masu (ASP-DAC, 2007)

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. - Takashi Sato 001; Takumi Uezono; Shiho Hagiwara; Kenichi Okada 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu (ISQED, 2007)

Adaptable wire-length distribution with tunable occupation probability. - Shuhei Amakawa; Takumi Uezono; Takashi Sato 001; Kenichi Okada 001; Kazuya Masu (SLIP, 2007)

LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. - Akiko Mineyama; Hiroyuki Ito; Takahiro Ishii; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2008)

A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. - Hong Phuc Ninh; Takashi Moue; Takashi Kurashina; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2008)

Small-area CMOS RF distributed mixer using multi-port inductors. - Susumu Sadoshima; Satoshi Fukuda; Tackya Yammouch; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2008)

Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. - Shoichi Hara; Takeshi Ito; Kenichi Okada 001; Akira Matsuzawa (ISCAS, 2008)

Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators. - Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2008)

Analysis of CMOS Transconductance Amplifiers for Sampling Mixers. - Ning Li 009; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2008)

Reconfigurable RF CMOS Circuit for Cognitive Radio. - Kazuya Masu; Kenichi Okada 001 (IEICE Trans. Commun., 2008)

A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. - Hiroyuki Ito; Makoto Kimura; Kazuya Miyashita; Takahiro Ishii; Kenichi Okada 001; Kazuya Masu (IEEE J. Solid State Circuits, 2008)

Physical Modeling of MEMS Variable Inductor. - Tackya Yammouch; Kenichi Okada 001; Kazuya Masu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. - Hirotaka Sugawara; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits. - Takeshi Ito; Kenichi Okada 001; Kazuya Masu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. - Daisuke Imanishi; Jee Young Hong; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2010)

A 60GHz direct-conversion transmitter in 65nm CMOS technology. - Naoki Takayama; Kota Matsushita; Shogo Ito; Ning Li 009; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2010)

A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. - Ning Li 009; Keigo Bunsen; Naoki Takayama; Qinghong Bu; Toshihide Suzuki; Masaru Sato 001; Tatsuya Hirose; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2010)

The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique. - Shoichi Hara; Rui Murakami; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider. - Shoichi Hara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2010)

Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design. - Ning Li 009; Kota Matsushita; Naoki Takayama; Shogo Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators. - Rui Murakami; Shoichi Hara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2010)

A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling. - Naoki Takayama; Kota Matsushita; Shogo Ito; Ning Li 009; Keigo Bunsen; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2010)

A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver. - Kenichi Okada 001 (ASICON, 2011)

A new figure of Merit of LC oscilators considering frequency tuning range. - Takahiro Sato; Kenichi Okada 001; Akira Matsuzawa (ASICON, 2011)

An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2011)

A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. - Ahmed Musa; Rui Murakami; Takahiro Sato; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2011)

A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS. - Hiroki Asada; Keigo Bunsen; Kota Matsushita; Rui Murakami; Qinghong Bu; Ahmed Musa; Takahiro Sato; Tatsuya Yamaguchi; Ryo Minami; Toshihiko Ito; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2011)

A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing. - Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2011)

A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2011)

A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. - Kenichi Okada 001; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Ning Li 009; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (ISSCC, 2011)

A 14.3% PAE parallel class-A and AB 60GHz CMOS PA. - Ning Li 009; Kota Matsushita; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2011)

An ultra-compact LC-VCO using a stacked-spiral inductor. - Rui Murakami; Toshihiko Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2011)

Tunable CMOS Power Amplifiers for Reconfigurable Transceivers. - Jee Young Hong; Daisuke Imanishi; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. - Shouhei Kousai; Daisuke Miyashita; Junji Wadatsumi; Rui Ito; Takahiro Sekiguchi; Mototsugu Hamada; Kenichi Okada 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving. - Ning Li 009; Qinghong Bu; Kota Matsushita; Naoki Takayama; Shogo Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2011)

Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip. - Ryo Minami; Jee Young Hong; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2011)

Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate. - Yuya Ono; Takuichi Hirano; Kenichi Okada 001; Jiro Hirokawa; Makoto Ando (IEICE Trans. Electron., 2011)

A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers. - Yusaku Ito; Kenichi Okada 001; Kazuya Masu (J. Electr. Comput. Eng., 2011)

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications. - Ahmed Musa; Rui Murakami; Takahiro Sato; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2011)

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. - Kenichi Okada 001; Ning Li 009; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (IEEE J. Solid State Circuits, 2011)

A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. - Ryo Minami; Hiroki Asada; Ahmed Musa; Takahiro Sato; Ning Li 009; Tatsuya Yamaguchi; Yasuaki Takeuchi; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios. - Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2012)

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (ISSCC, 2012)

Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design. - Qinghong Bu; Ning Li 009; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning. - Jee Young Hong; Daisuke Imanishi; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

Inter-Stage Tunable Notch Filter for a Multi-Band WCDMA Receiver. - Toshihiko Ito; Masaki Kanemaru; Satoshi Furuya; Dong Ta Ngoc Huy; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A Wideband Common-Gate Low-Noise Amplifier Using Capacitive Feedback. - Toshihiko Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. - Ning Li 009; Keigo Bunsen; Naoki Takayama; Qinghong Bu; Toshihide Suzuki; Masaru Sato 001; Yoichi Kawano; Tatsuya Hirose; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A Dual-Conduction Class-C VCO for a Low Supply Voltage. - Kenichi Okada 001; You Nomiyama; Rui Murakami; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Clock/Frequency Generation Circuits and Systems. - Woogeun Rhee; Antonio Liscidini; Jae-Yoon Sim; Kenichi Okada 001; Sudhakar Pamarti (J. Electr. Comput. Eng., 2012)

A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. - Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A full 4-channel 60 GHz direct-conversion transceiver. - Seitaro Kawai; Ryo Minami; Ahmed Musa; Takahiro Sato; Ning Li 009; Tatsuya Yamaguchi; Yasuaki Takeuchi; Yuki Tsukui; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2013)

A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2013)

Session 13 overview: High-performance wireless. - Brian A. Floyd; Kenichi Okada 001 (ISSCC, 2013)

A 60 GHz up-conversion mixer using asymmetric layout with -41.1 dBc LO leakage. - Yuki Tsukui; Kenichi Okada 001; Akira Matsuzawa (LASCAS, 2013)

A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate. - Hamid Kiumarsi; Hiroyuki Ito; Kenichi Okada 001; Yusuke Uemichi; Yasuto Chiba; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2013)

A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs. - Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. - Teerachot Siriburanon; Takahiro Sato; Ahmed Musa; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2013)

Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2013)

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2013)

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (IEEE J. Solid State Circuits, 2013)

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2014)

A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs. - Rui Wu 001; Qinghong Bu; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2014)

A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. - Aravind Tharayil Narayanan; Kento Kimura; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2014)

15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. - Masaya Miyahara; Ibuki Mano; Masaaki Nakayama; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. - Kenichi Okada 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Yasuaki Takeuchi; Tatsuya Yamaguchi; Ahmed Musa; Rui Wu 001; et al. (ISSCC, 2014)

F4: Mm-Wave advances for active safety and communication systems. - Marc Tiebout; Brian A. Floyd; Mike Keaveney; Pierre Busson; Kenichi Okada 001 (ISSCC, 2014)

A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation. - Rui Wu 001; Yuuki Tsukui; Ryo Minami; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2014)

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. - Wei Deng 001; Shoichi Hara; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. - Ahmed Musa; Wei Deng 001; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A 28-Gb/s 60-GHz wireless transceiver in 65nm CMOS with 64QAM capability. - Kenichi Okada 001 (ASICON, 2015)

A tail-current modulated VCO with adaptive-bias scheme. - Aravind Tharayil Narayanan; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. - Teerachot Siriburanon; Tomohiro Ueno; Kento Kimura; Satoshi Kondo; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

An HDL-synthesized gated-edge-injection PLL with a current output DAC. - Dongsheng Yang 002; Wei Deng 001; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Korkut Kaan Tokgoz; Kengo Nakata; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2015)

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. - Teerachot Siriburanon; Hanli Liu; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2015)

Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process. - Ning Li 009; Takeshi Inoue; Takuichi Hirano; Jian Pang; Rui Wu 001; Kenichi Okada 001; Hitoshi Sakane; Akira Matsuzawa (ESSDERC, 2015)

14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. - Wei Deng 001; Dongsheng Yang 002; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

19.5 An HCI-healing 60GHz CMOS transceiver. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; Yasuaki Takeuchi; Tatsuya Yamaguchi; et al. (ISSCC, 2015)

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Rui Wu 001; Bangan Liu; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2015)

An AM-PM Noise Mitigation Technique in Class-C VCO. - Kento Kimura; Aravind Tharayil Narayanan; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

Digitally Assisted Analog and RF Circuits. - Kenichi Okada 001 (IEICE Trans. Electron., 2015)

A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design. - Korkut Kaan Tokgoz; Kimsrun Lim; Seitarou Kawai; Nurul Fajri; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. - Rui Wu 001; Wei Deng 001; Shinji Sato; Takuichi Hirano; Ning Li 009; Takeshi Inoue; Hitoshi Sakane; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC). - Angelo Nagari; Kenichi Okada 001; Marian Verhelst (IEEE J. Solid State Circuits, 2015)

Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. - Makoto Takamiya; Jieh-Tsorng Wu; Jussi Ryynänen; Kenichi Okada 001; Jaeha Kim (IEEE J. Solid State Circuits, 2015)

A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kengo Nakata; Yuki Terashima; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. - Rui Wu 001; Jian Pang; Yuuki Seo; Kento Kimura; Seitaro Kawai; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Yasuaki Takeuchi; Tatsuya Yamaguchi; Ahmed Musa; et al. (A-SSCC, 2016)

A 2 GHz 3.1 mW type-I digital ring-based PLL. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

Session 26 overview: Wireless for IoE. - Kenichi Okada 001; Jan van Sinderen (ISSCC, 2016)

F3: Radio architectures and circuits towards 5G. - Stefano Pellerano; Ahmad Mirzaei; Chih-Ming Hung; Jan Craninckx; Kenichi Okada 001; Vojkan Vidojkovic (ISSCC, 2016)

13.3 A 56Gb/s W-band CMOS wireless transceiver. - Korkut Kaan Tokgoz; Shotaro Maki; Seitaro Kawai; Noriaki Nagashima; Jun Emmei; Masato Dome; Hisashi Kato; Jian Pang; Yoichi Kawano; Toshihide Suzuki; Taisuke Iwai; Yuuki Seo; et al. (ISSCC, 2016)

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Nurul Fajri; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Teerachot Siriburanon; Shoutarou Maki; Bangan Liu; Yun Wang 008; et al. (ISSCC, 2016)

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. - Mitsutoshi Sugawara; Kenji Mori; Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. - Dongsheng Yang 002; Tomohiro Ueno; Wei Deng 001; Yuki Terashima; Kengo Nakata; Aravind Tharayil Narayanan; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2016)

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Korkut Kaan Tokgoz; Kengo Nakata; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. - Teerachot Siriburanon; Satoshi Kondo; Makihiko Katsuragi; Hanli Liu; Kento Kimura; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. - Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (ASICON, 2017)

W-band ultra-high data-rate 65nm CMOS wireless transceiver. - Korkut Kaan Tokgoz; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yoichi Kawano; Toshihide Suzuki; Taisuke Iwai; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Aravind Tharayil Narayanan; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. - Huy Cu Ngo; Kengo Nakata; Toru Yoshioka; Yuki Terashima; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2017)

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (ISSCC, 2017)

Analysis of Effective Material Properties of Metal Dummy Fills in a CMOS Chip. - Takuichi Hirano; Ning Li 009; Kenichi Okada 001 (IEICE Trans. Commun., 2017)

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS. - Yun Wang 008; Makihiko Katsuragi; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2017)

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (IEEE J. Solid State Circuits, 2017)

A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay. - Jian Pang; Korkut Kaan Tokgoz; Shotaro Maki; Zheng Li 021; Xueting Luo; Ibrahim Abdo; Seitarou Kawai; Hanli Liu; Bangan Liu; Makihiko Katsuragi; Kento Kimura; Atsushi Shirane; et al. (A-SSCC, 2018)

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. - Bangan Liu; Huy Cu Ngo; Kengo Nakata; Wei Deng 001; Yuncheng Zhang; Junjun Qiu; Toru Yoshioka; Jun Emmei; Haosheng Zhang; Jian Pang; Aravind Tharayil Narayanan; Dongsheng Yang 002; et al. (CICC, 2018)

A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver. - Zheng Sun 001; Hanli Liu; Dexian Tang; Hongye Huang; Tohru Kaneko; Rui Wu 001; Wei Deng 001; Kenichi Okada 001 (ESSCIRC, 2018)

An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Wei Deng 001; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. - Hanli Liu; Dexian Tang; Zheng Sun 001; Wei Deng 001; Huy Cu Ngo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. - Korkut Kaan Tokgoz; Shotaro Maki; Jian Pang; Noriaki Nagashima; Ibrahim Abdo; Seitaro Kawai; Takuya Fujimura; Yoichi Kawano; Toshihide Suzuki; Taisuke Iwai; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. - Masaya Miyahara; Yukiya Endo; Kenichi Okada 001; Akira Matsuzawa (VLSI Circuits, 2018)

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS. - Korkut Kaan Tokgoz; Seitaro Kawai; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2018)

A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. - Hanli Liu; Teerachot Siriburanon; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. - Bangan Liu; Yun Wang 008; Jian Pang; Haosheng Zhang; Dongsheng Yang 002; Aravind Tharayil Narayanan; Dae Young Lee; Sung Tae Choi; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)

Foreword. - Kenichi Okada 001 (IEICE Trans. Electron., 2018)

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Zhijie Chen; Wei Deng 001; Rui Wu 001; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2018)

A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. - Hanli Liu; Dexian Tang; Zheng Sun 001; Wei Deng 001; Huy Cu Ngo; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2018)

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. - Yuji Yano; Seiya Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Tetsuya Hirose; Masaya Miyahara; Teruki Someya; Kenichi Okada 001; Ippei Akita; Yoshihiko Kurui; Hideyuki Tomizawa; Masahiko Yoshimoto (A-SSCC, 2019)

300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology. - Hiroshi Hamada; Takuya Tsutsumi; Go Itami; Hiroki Sugiyama; Hideaki Matsuzaki; Kenichi Okada 001; Hideyuki Nosaka (BCICTS, 2019)

Millimeter-Wave CMOS Phased-Array Transceiver Toward 1Tbps Wireless Communication. - Kenichi Okada 001 (BCICTS, 2019)

An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Wei Deng 001; Zule Xu; Haosheng Zhang; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (CICC, 2019)

Millimeter-Wave CMOS Transceiver Toward 1Tbps Wireless Communication. - Korkut Kaan Tokgoz; Kenichi Okada 001 (ISCAS, 2019)

A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2019)

A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (ISSCC, 2019)

Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping. - Haosheng Zhang; Hans Herdian; Aravind Tharayil Narayanan; Atsushi Shirane; Mitsuru Suzuki; Kazuhiro Harasaka; Kazuhiko Adachi; Shinya Yanagimachi; Kenichi Okada 001 (ISSCC, 2019)

0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. - Haosheng Zhang; Aravind Tharayil Narayanan; Hans Herdian; Bangan Liu; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (VLSI Circuits, 2019)

A Pulse-Tail-Feedback LC-VCO with 700Hz Flicker Noise Corner and -195dBc FoM. - Aravind Tharayil Narayanan; Kenichi Okada 001 (IEICE Trans. Electron., 2019)

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2019)

A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock. - Haosheng Zhang; Aravind Tharayil Narayanan; Hans Herdian; Bangan Liu; Rui Wu 001; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2019)

A 265- $ mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. - Hanli Liu; Atsushi Shirane; Kenichi Okada 001; Zheng Sun 001; Hongye Huang; Wei Deng 001; Teerachot Siriburanon; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya (IEEE J. Solid State Circuits, 2019)

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (IEEE J. Solid State Circuits, 2019)

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio. - Jian Pang; Rui Wu 001; Yun Wang 008; Masato Dome; Hisashi Kato; Hongye Huang; Aravind Tharayil Narayanan; Hanli Liu; Bangan Liu; Takeshi Nakamura; Takuya Fujimura; Masaru Kawabuchi; et al. (IEEE J. Solid State Circuits, 2019)

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. - Yun Wang 008; Bangan Liu; Rui Wu 001; Hanli Liu; Aravind Tharayil Narayanan; Jian Pang; Ning Li 009; Toru Yoshioka; Yuki Terashima; Haosheng Zhang; Dexian Tang; Makihiko Katsuragi; et al. (IEEE J. Solid State Circuits, 2019)

ULPAC: A Miniaturized Ultralow-Power Atomic Clock. - Haosheng Zhang; Hans Herdian; Aravind Tharayil Narayanan; Atsushi Shirane; Mitsuru Suzuki; Kazuhiro Harasaka; Kazuhiko Adachi; Shigeyoshi Goka; Shinya Yanagimachi; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2019)

A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. - Zheng Li 021; Jian Pang; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Joshua Alvin; Bangan Liu; Zheng Sun 001; Hongye Huang; et al. (ASP-DAC, 2020)

Millimeter-Wave CMOS Phased-Array Transceiver Supporting Dual-Polarized MIMO for 5G NR. - Kenichi Okada 001; Jian Pang (CICC, 2020)

A Compact 37-40GHz CMOS Switch-Type Phase Shifter with Fine-Tuning Stage Achieving 0.4-dB RMS Gain Error. - Jian Pang; Xueting Luo; Zheng Li 021; Atsushi Shirane; Kenichi Okada 001 (ICTA, 2020)

Wireless Devices Identification with Light-Weight Convolutional Neural Network Operating on Quadrant IQ Transition Image. - Hiro Tamura; Kiyoshi Yanagisawa; Atsushi Shirane; Kenichi Okada 001 (NEWCAS, 2020)

A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (VLSI Circuits, 2020)

A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. - Yuncheng Zhang; Bangan Liu; Xiaofan Gu; Chun Wang; Kiyoshi Yanagisawa; Junjun Qiu; Yun Wang 008; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (VLSI Circuits, 2020)

A 28-GHz CMOS Vector-Summing Phase Shifter Featuring I/Q Imbalance Calibration Supporting 11.2Gb/s in 256QAM for 5G New Radio. - Jian Pang; Ryo Kubozoe; Zheng Li 021; Masaru Kawabuchi; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2020)

A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. - Zheng Sun 001; Dingxin Xu; Hongye Huang; Zheng Li 021; Hanli Liu; Bangan Liu; Jian Pang; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2020)

300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers. - Hiroshi Hamada; Takuya Tsutsumi; Hideaki Matsuzaki; Takuya Fujimura; Ibrahim Abdo; Atsushi Shirane; Kenichi Okada 001; Go Itami; Ho-Jin Song; Hiroki Sugiyama; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2020)

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (IEEE J. Solid State Circuits, 2020)

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS. - Yun Wang 008; Rui Wu 001; Jian Pang; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Xi Fu; Daiki Matsumoto; Takeshi Nakamura; Ryo Kubozoe; Masaru Kawabuchi; Bangan Liu; et al. (IEEE J. Solid State Circuits, 2020)

A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver. - Ibrahim Abdo; Takuya Fujimura; Tsuyoshi Miura; Korkut Kaan Tokgoz; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2021)

A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System. - Joshua Alvin; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2021)

A DSM-based Polar Transmitter with 23.8% System Efficiency. - Yuncheng Zhang; Bangan Liu; Xiaofan Gu; Chun Wang; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2021)

28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver. - Yi Zhang 092; Jian Pang; Kiyoshi Yanagizawa; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2021)

A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. - Zheng Sun 001; Dingxin Xu; Junjun Qiu; Zezheng Liu; Yuncheng Zhang; Hongye Huang; Hanli Liu; Bangan Liu; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2021)

Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate. - Hans Herdian; Takeshi Inoue; Takuichi Hirano; Masatsugu Sogabe; Atsushi Shirane; Kenichi Okada 001 (ESSDERC, 2021)

A 28GHz Bi-direction Transceiver with Temperature Compensation. - Yi Zhang 092; Jian Pang; Zheng Li 021; Atsushi Shirane; Kenichi Okada 001 (ICTA, 2021)

A 39GHz Divide-by-8 LC-Ring ILFD Designed for 5G New Radio n260 Band. - Yudai Yamazaki; Joshua Alvin; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ICTA, 2021)

22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS. - Ibrahim Abdo; Carrel da Gomez; Chun Wang; Kota Hatano; Qi Li 061; Chenxin Liu; Kiyoshi Yanagisawa; Ashbir Aviat Fadila; Jian Pang; Hiroshi Hamada; Hideyuki Nosaka; Atsushi Shirane; et al. (ISSCC, 2021)

32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2021)

A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter with 24-GHz Wireless Power and LO Transfer. - Michihiro Ide; Atsushi Shirane; Kiyoshi Yanagisawa; Dongwon You; Jian Pang; Kenichi Okada 001 (VLSI Circuits, 2021)

A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Weichu Chen; Yun Wang 008; Dongwon You; et al. (VLSI Circuits, 2021)

64QAM wireless link with 300GHz InP-CMOS hybrid transceiver. - Ibrahim Abdo; Hiroshi Hamada; Hideyuki Nosaka; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2021)

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (IEEE J. Solid State Circuits, 2021)

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Jian Pang; Hanli Liu; Masaya Miyahara; et al. (IEEE J. Solid State Circuits, 2021)

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Huy Cu Ngo; Wei Deng 001; Kengo Nakata; Toru Yoshioka; Jun Emmei; Jian Pang; Aravind Tharayil Narayanan; Haosheng Zhang; Teruki Someya; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch. - Zheng Sun 001; Hanli Liu; Hongye Huang; Dexian Tang; Dingxin Xu; Tohru Kaneko; Zheng Li 021; Jian Pang; Rui Wu 001; Wei Deng 001; Atsushi Shirane; Kenichi Okada 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 220-294 GHz Power Amplifier with 10-dBm Psat and 2.2% PAE in 250-nm InP DHBT. - Teruo Jyo; Hiroshi Hamada; Munehiko Nagatani; Hitoshi Wakita; Ibrahim Abdo; Miwa Mutoh; Yuta Shiratori; Kenichi Okada 001; Atsushi Shirane; Hiroyuki Takahashi (BCICTS, 2022)

Maximizing Energy Efficiency in Sub-THz Radio Communication and Prospective toward 6G. - Kenichi Okada 001 (BCICTS, 2022)

A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay Transceivers. - Sena Kato; Keito Yuasa; Michihiro Ide; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2022)

A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio. - Minzhe Tang; Yi Zhang 092; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2022)

A 1.8-67GHz Divide-by-4 ILFD Using Area-Efficient Transformer-Based Injection-Enhancing Technique. - Yudai Yamazaki; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2022)

A 41-GHz 19.4-dBm PSATCMOS Doherty Power Amplifier for 5G NR Applications. - Zheng Li 021; Zixin Chen; Qiaoyu Wang; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ICTA, 2022)

A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation. - Xi Fu; Yun Wang 008; Dongwon You; Xiaolin Wang; Ashbir Aviat Fadila; Yi Zhang 092; Sena Kato; Chun Wang; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2022)

A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR. - Jian Pang; Yi Zhang 092; Zheng Li 021; Minzhe Tang; Yijing Liao; Ashbir Aviat Fadila; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2022)

Millimeter-Wave CMOS Phased-Array Transceivers for 5G and Beyond. - Kenichi Okada 001; Jian Pang; Atsushi Shirane; Zheng Li 021; Yi Zhang 092; Naoki Oshima; Shinichi Hori; Kazuaki Kunihiro (PIMRC, 2022)

A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer. - Michihiro Ide; Yuasa Keito; Sena Kato; Dongwon You; Ashbir Aviat Fadila; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (VLSI Technology and Circuits, 2022)

A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station. - Zheng Li 021; Jian Pang; Yi Zhang 092; Yudai Yamazaki; Qiaoyu Wang; Peng Luo; Weichu Chen; Yijing Liao; Minzhe Tang; Zhengyan Guo; Yun Wang 008; Xi Fu; et al. (VLSI Technology and Circuits, 2022)

A low-power digital baseband circuit for GMSK demodulation in sub-GHz application. - Junjun Qiu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2022)

Performance Evaluation of Classification and Verification with Quadrant IQ Transition Image. - Hiro Tamura; Kiyoshi Yanagisawa; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Commun., 2022)

F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power. - Ibrahim Abdo; Korkut Kaan Tokgoz; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2022)

A Compact and High-Resolution CMOS Switch-Type Phase Shifter Achieving 0.4-dB RMS Gain Error for 5G n260 Band. - Jian Pang; Xueting Luo; Zheng Li 021; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2022)

A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components. - Yuncheng Zhang; Bangan Liu; Teruki Someya; Rui Wu 001; Junjun Qiu; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2022)

A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. - Ibrahim Abdo; Carrel da Gomez; Chun Wang; Kota Hatano; Qi Li 061; Chenxin Liu; Kiyoshi Yanagisawa; Ashbir Aviat Fadila; Takuya Fujimura; Tsuyoshi Miura; Korkut Kaan Tokgoz; Jian Pang; et al. (IEEE J. Solid State Circuits, 2022)

A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. - Yun Wang 008; Dongwon You; Xi Fu; Takeshi Nakamura; Ashbir Aviat Fadila; Teruki Someya; Atsuhiro Kawaguchi; Junjun Qiu; Jian Pang; Kiyoshi Yanagisawa; Bangan Liu; Yuncheng Zhang; et al. (IEEE J. Solid State Circuits, 2022)

A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR. - Yi Zhang 092; Jian Pang; Zheng Li 021; Minzhe Tang; Yijing Liao; Ashbir Aviat Fadila; Atsushi Shirane; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2022)

An 8.5-dB Insertion Loss and 0.8° RMS Phase Error Ka-Band CMOS Hybrid Phase Shifter Featuring Nonuniform Matching for Satellite Communication. - Xi Fu; Yun Wang 008; Xiaolin Wang; Xiaofan Gu; Xueting Luo; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2022)

A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (CICC, 2023)

A 24-49-GHz CMOS Area-Efficient Phase-Invariant Mixed-Type Attenuator With Capacitive Compensation for 5G New Radio. - Zheng Li 021; Peng Luo; Jian Pang; Qiaoyu Wang; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2023)

A Dual-Mode Bi-Directional CMOS Mixer Using Push-Push Doubler for 300GHz-Band Transceivers. - Chenxin Liu; Ibrahim Abdo; Chun Wang; Hiroyuki Sakai 009; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2023)

A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2023)

A 60-GHz Transformer-Based Power Amplifier Supporting 5G n263-band Applications. - Junqing Liu; Zheng Li 021; Minghao Fan; Yilun Chen; Atsushi Shirane; Kenichi Okada 001 (ICICDT, 2023)

A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation. - Xi Fu; Dongwon You; Xiaolin Wang; Michihiro Ide; Yuncheng Zhang; Jun Sakamaki; Ashbir Aviat Fadila; Zheng Li 021; Yun Wang 008; Jumpei Sudo; Makoto Higaki; Soichiro Inoue; et al. (ISSCC, 2023)

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. - Junjun Qiu; Wenqian Wang; Zheng Sun 001; Bangan Liu; Yuncheng Zhang; Dingxin Xu; Hongye Huang; Ashbir Aviat Fadila; Zezheng Liu; Waleed Madany; Yuang Xiong; Atsushi Shirane; et al. (ISSCC, 2023)

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler. - Dongwon You; Xi Fu; Xiaolin Wang; Yuan Gao; Wenqian Wang; Jun Sakamaki; Hans Herdian; Sena Kato; Michihiro Ide; Yuncheng Zhang; Ashbir Aviat Fadila; Zheng Li 021; et al. (ISSCC, 2023)

A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression. - Chun Wang; Ibrahim Abdo; Chenxin Liu; Carrel da Gomez; Hans Herdian; Wenqian Wang; Xi Fu; Dongwon You; Abanob Shehata; Sunghwan Park; Yun Wang 008; Jian Pang; et al. (VLSI Technology and Circuits, 2023)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (VLSI Technology and Circuits, 2023)

A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount. - Dongwon You; Xiaolin Wang; Hans Herdian; Xi Fu; Hojun Lee; Michihiro Ide; Carrel da Gomez; Zheng Li 021; Jill C. Mayeda; Daisuke Awaji; Jian Pang; Hiraku Sakamoto; et al. (IEEE Access, 2023)

A 41-GHz 19.4-dBm Psat CMOS Doherty power amplifier for 5G NR applications. - Zheng Li 021; Zixin Chen; Qiaoyu Wang; Junqing Liu; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2023)

A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station. - Zheng Li 021; Jian Pang; Yi Zhang 092; Yudai Yamazaki; Qiaoyu Wang; Peng Luo; Weichu Chen; Yijing Liao; Minzhe Tang; Yun Wang 008; Xi Fu; Dongwon You; et al. (IEEE J. Solid State Circuits, 2023)

A 28GHz High-Accuracy Phase and Amplitude Detection Circuit for Dual-Polarized Phased-Array Calibration. - Yudai Yamazaki; Joshua Alvin; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2023)

A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD. - Yudai Yamazaki; Jun Sakamaki; Jian Pang; Joshua Alvin; Zheng Li 021; Dongwon You; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2023)

A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations. - Xi Fu; Dongwon You; Xiaolin Wang; Yun Wang 008; Carolyn Jill Mayeda; Yuan Gao; Michihiro Ide; Yuncheng Zhang; Jun Sakamaki; Ashbir Aviat Fadila; Zheng Li 021; Jumpei Sudo; et al. (IEEE J. Solid State Circuits, 2023)

35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers. - Abanob Shehata; Hans Herdian; Chun Wang; Chenxin Liu; Kazuaki Kunihiro; Hiroyuki Sakai 009; Atsushi Shirane; Kenichi Okada 001 (A-SSCC, 2024)

A Compact D-Band Phase Shifter with 0.1-degree Phase Resolution and 0.8-degree RMS Phase Error in 65 nm CMOS. - Takaya Uchino; Yudai Yamazaki; Sunghwan Park; Chenxin Liu; Anyi Tian; Abanob Shehata; Hiroyuki Sakai 009; Kazuaki Kunihiro; Atsushi Shirane; Kenichi Okada 001 (A-SSCC, 2024)

300-GHz-Band InP HBT Power Amplifier and InP-CMOS Hybrid Phased-Array Transmitter. - Teruo Jyo; Ibrahim Abdo; Hiroshi Hamada; Munehiko Nagatani; Adam Pander; Hitoshi Wakita; Miwa Mutoh; Yuta Shiratori; Daisuke Kitayama; Carrel da Gomez; Chun Wang; Kota Hatano; et al. (BCICTS, 2024)

Sub-THz CMOS Phased-Array Transceiver Design for 6G. - Kenichi Okada 001 (ISCAS, 2024)

A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases. - Sidharth Thomas; Jaskirat Singh Virdi; Anshul Verma; Bishnu Prasad Das; Kenichi Okada 001; Pratap Narayan Singh (ISCAS, 2024)

A 24-71-GHz Tri-Mode Mixer Using Harmonic Selection for Multi-Band 5G NR. - Dongfan Xu; Minzhe Tang; Yi Zhang 092; Zheng Li 021; Atsushi Shirane; Kenichi Okada 001 (ISCAS, 2024)

24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS. - Chun Wang; Hans Herdian; Wenbin Zheng; Chenxin Liu; Jill C. Mayeda; Yuxuan Liu; Olivia Angel Yong; Wenqian Wang; Yuncheng Zhang; Carrel da Gomez; Abanob Shehata; Sena Kato; et al. (ISSCC, 2024)

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (ISSCC, 2024)

A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer. - Sena Kato; Shu Date; Tao Ruoxin; Yasuto Narukiyo; Hiroki Hayashi; Keito Yuasa; Michihiro Ide; Takashi Tomura; Kenichi Okada 001; Atsushi Shirane (VLSI Technology and Circuits, 2024)

A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (VLSI Technology and Circuits, 2024)

A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond. - Yi Zhang 092; Minzhe Tang; Jian Pang; Zheng Li 021; Dongfan Xu; Dingxin Xu; Yuncheng Zhang; Kazuaki Kunihiro; Hiroyuki Sakai 009; Atsushi Shirane; Kenichi Okada 001 (VLSI Technology and Circuits, 2024)

A synthesizable spread spectrum clock generator based on type-II/III fractional-N DPLL. - Waleed Madany; Hongye Huang; Bangan Liu; Ashbir Aviat Fadila; Zezheng Liu; Wenqian Wang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2024)

Millimeter-Wave Transceiver Utilizing On-Chip Butler Matrix for Simultaneous 5G Relay Communication and Wireless Power Transfer. - Keito Yuasa; Michihiro Ide; Sena Kato; Kenichi Okada 001; Atsushi Shirane (IEICE Trans. Electron., 2024)

Design of Synthesizable Digital Phase Locked Loops. - Yuncheng Zhang; Kenichi Okada 001 (IPSJ Trans. Syst. LSI Des. Methodol., 2024)

A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation. - Xi Fu; Dongwon You; Yun Wang 008; Xiaolin Wang; Ashbir Aviat Fadila; Chenxin Liu; Sena Kato; Chun Wang; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2024)

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression. - Chun Wang; Ibrahim Abdo; Chenxin Liu; Carrel da Gomez; Jill C. Mayeda; Hans Herdian; Wenqian Wang; Xi Fu; Dongwon You; Abanob Shehata; Sunghwan Park; Yun Wang 008; et al. (IEEE J. Solid State Circuits, 2024)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (IEEE J. Solid State Circuits, 2024)

Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium. - Kenichi Okada 001 (IEEE J. Solid State Circuits, 2024)

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (ASP-DAC, 2025)

A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NR. - Dongfan Xu; Minzhe Tang; Yi Zhang 092; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2025)

A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate. - Yi Zhang 092; Minzhe Tang; Zheng Li 021; Dongfan Xu; Kazuaki Kunihiro; Hiroyuki Sakai 009; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2025)

A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter. - Daxu Zhang; Dingxin Xu; Hongye Huang; Waleed Madany; Zezheng Liu; Wenqian Wang; Yuang Xiong; Ashbir Aviat Fadila; Duo Li; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (CICC, 2025)

11.1 A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite Constellations. - Sena Kato; Jill C. Mayeda; Keito Yuasa; Michihiro Ide; Takeshi Ota; Shu Date; Yudai Yamazaki; Xiaolin Wang; Xi Fu; Dongwon You; Makoto Higaki; Jumpei Sudo; et al. (ISSCC, 2025)

5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM. - Yuncheng Zhang; Zezheng Liu; Duo Li; Minzhe Tang; Yi Zhang 092; Hongye Huang; Dingxin Xu; Waleed Madany; Ashbir Aviat Fadila; Wenqian Wang; Yuang Xiong; Daxu Zhang; et al. (ISSCC, 2025)

Millimeter-wave GaAs Rectifier with Differential Signal 4:1 Power Combiner for Simultaneous Wireless Information and Power Transmission. - Masayuki Kikuchi; Michihiro Ide; Jill C. Mayeda; Sena Kato; Keito Yuasa; Kenichi Okada 001; Atsushi Shirane (LASCAS, 2025)

NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers. - Hongye Huang; Ashbir Aviat Fadila; Dingxin Xu; Waleed Madany; Wenqian Wang; Zezheng Liu; Yuang Xiong; Tianshi Hu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A LEO Satellite Mounted 256-Element 19 GHz CMOS Phased-Array Transmitter With On-Chip Amplitude and Phase Monitor. - Xiaolin Wang; Dongwon You; Xi Fu; Gao Yuan; Takeshi Ota; Jill C. Mayeda; Jun Sakamaki; Ashbir Aviat Fadila; Makoto Higaki; Jumpei Sudo; Hiroshi Takizawa; Masashi Shirakura; et al. (IEEE Access, 2025)

A 2.5 dB noise figure 28 GHz current-reused noise-cancelling LNA with gm-boosting in 65 nm CMOS for millimeter-wave MIMO applications. - Yi Zhang 092; Minzhe Tang; Dongfan Xu; Jian Pang; Hiroyuki Sakai 009; Kazuaki Kunihiro; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2025)

Millimeter-Wave Wirelessly-Powered Phased-Array Relay Transceiver Utilizing CMOS Switching Rectifier-Type Mixer. - Sena Kato; Keito Yuasa; Michihiro Ide; Kenichi Okada 001; Atsushi Shirane (IEICE Trans. Electron., 2025)

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (IEEE J. Solid State Circuits, 2025)

A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (IEEE J. Solid State Circuits, 2025)

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (IEEE J. Solid State Circuits, 2025)

A Compact D-Band Phase Shifter With 0.1-Degree Phase Resolution and Ultra-Low Phase Error in 65-nm CMOS. - Takaya Uchino; Yudai Yamazaki; Anyi Tian; Chenxin Liu; Sunghwan Park; Abanob Shehata; Sena Kato; Takumi Kojima; Haruto Tanaka; Masayuki Kikuchi; Jill C. Mayeda; Ryuji Kinugawa; et al. (IEEE J. Solid State Circuits, 2025)