A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. - Hiroyuki Mizuno; Nozomu Matsuzaki; Kenichi Osada; Toshinobu Shinbo; Nagatoshi Ohki; Hiroshi Ishida; Koichiro Ishibashi; Tokuo Kure (IEEE J. Solid State Circuits, 1996)

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. - Kenichi Osada; Jinuk Luke Shin; Masood Khan; Yude Liou; Karl Wang; Kenichi Shoji; Kenichi Kuroda; Shuji Ikeda; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2001)

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. - Kenichi Osada; Yoshikazu Saitoh; Eishi Ibe; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2003)

Reviews and future prospects of low-voltage embedded RAMs. - Kiyoo Itoh 001; Kenichi Osada; Takayda Kawahara (CICC, 2004)

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. - Kenichi Osada; Naoki Kitai; Shiro Kamohara; Takayuki Kawahara (CICC, 2004)

Low-Voltage Embedded RAMs - Current Status and Future Trends. - Kiyoo Itoh 001; Kenichi Osada; Takayuki Kawahara (PATMOS, 2004)

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. - Kenichi Osada; Ken Yamaguchi; Yoshikazu Saitoh; Takayuki Kawahara (IEEE J. Solid State Circuits, 2004)

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. - Masanao Yamaoka; Kenichi Osada; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2004)

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. - Kenichi Osada; Takayuki Kawahara; Riichiro Takemura; Naoki Kitai; Norikatsu Takaura; Nozomu Matsuzaki; Kenzo Kurotsuchi; Hiroshi Moriya; Masahiro Moniwa (CICC, 2005)

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. - Akira Kotabe; Kenichi Osada; Naoki Kitai; Mio Fujioka; Shiro Kamohara; Masahiro Moniwa; Sadayuki Morita; Yoshikazu Saitoh (IEEE J. Solid State Circuits, 2005)

A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. - Masanao Yamaoka; Yoshihiro Shinozaki; Noriaki Maeda; Yasuhisa Shimazaki; Kei Kato; Shigeru Shimada; Kazumasa Yanagisawa; Kenichi Osada (IEEE J. Solid State Circuits, 2005)

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. - Satoru Hanzawa; Naoki Kitai; Kenichi Osada; Akira Kotabe; Yuichi Matsui; Nozomu Matsuzaki; Norikatsu Takaura; Masahiro Moniwa; Takayuki Kawahara (ISSCC, 2007)

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. - Makoto Saen; Kenichi Osada; Satoshi Misaka; Tetsuya Yamada; Yoshitaka Tsujimoto; Yuki Kondo; Tatsuya Kamei; Yutaka Yoshida; Ei Nagahama; Yusuke Nitta; Takayasu Ito; Tadashi Kameyama; et al. (ISSCC, 2007)

A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. - Masanao Yamaoka; Kenichi Osada; Takayuki Kawahara (ESSCIRC, 2008)

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. - Masanao Yamaoka; Noriaki Maeda; Yasuhisa Shimazaki; Kenichi Osada (ISSCC, 2008)

Memory at VLSI Circuits Symposium. - Kiyoo Itoh 001; Hideaki Kurata; Kenichi Osada; Tomonori Sekiguchi (IEEE J. Solid State Circuits, 2008)

A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. - Shigenobu Komatsu; Masanao Yamaoka; Masao Morimoto; Noriaki Maeda; Yasuhisa Shimazaki; Kenichi Osada (CICC, 2009)

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. - Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Makoto Saen; Shigenobu Komatsu; Kenichi Osada; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (ISSCC, 2009)

Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. - Kiyoto Ito; Makoto Saen; Kenichi Osada; Tomoyuki Kodama; Hiroyuki Mizuno (3DIC, 2010)

Development of a CAD tool for 3D-FPGAs. - Naoto Miyamoto; Yohei Matsumoto; Hanpei Koike; Tadayuki Matsumura; Kenichi Osada; Yaoko Nakagawa; Tadahiro Ohmi (3DIC, 2010)

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. - Makoto Saen; Kenichi Osada; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yoshinori Kohama; Yasufumi Sugimori; Kazutaka Kasuga; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2010)

6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV. - Futoshi Furuta; Kenichi Osada (3DIC, 2011)

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yasufumi Sugimori; Yoshinori Kohama; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors. - Kiyoto Ito; Makoto Saen; Kenichi Osada (IROS, 2012)

Fully digital voltage-mode control based on predictive hysteresis method (FDVC-PH) for DC-DC converters. - Ming Liu; Tatsuo Nakagawa; Kenichi Osada (ISCAS, 2012)

Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. - Yasuhiro Shinozuka; Hiroshi Fuketa; Koichi Ishida; Futoshi Furuta; Kenichi Osada; Kenichi Takeda; Makoto Takamiya; Takayasu Sakurai (ISQED, 2013)

A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. - Takashi Takemoto; Yasunobu Matsuoka; Yoshikazu Sugiyama; Hidenori Yonezawa; Hiroki Yamashita; Koichiro Adachi; Takahiro Nakamura; Etsuko Nomoto; Kouji Nakahara; Hideo Arimoto; Kenichi Osada; Tatemi Ido (OFC, 2015)