A macro analysis of soft errors in static RAMs. - Yasunobu Nakase; Kenji Anami; Tohru Shiomi; Atsushi Ohba; Shinpei Kayano (IEEE J. Solid State Circuits, 1988)

Improvement of soft-error rate in MOS SRAMs. - Shuji Murakami; Katsuki Ichinose; Kenji Anami; Shimpei Kayano (IEEE J. Solid State Circuits, 1989)

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture. - Toshihiko Hirose; Hirotada Kuriyama; Shuji Murakami; Kojiro Yuzuriha; Takao Mukai; Kazuhito Tsutsumi; Yasumasa Nishimura; Yoshio Kohno; Kenji Anami (IEEE J. Solid State Circuits, 1990)

Simple noise model and low-noise data-output buffer for ultrahigh-speed memories. - Tomohisa Wada; Masanao Eino; Kenji Anami (IEEE J. Solid State Circuits, 1990)

Variable bit organization as a new test function for standard memories. - Tomohisa Wada; Masanao Eino; Motomu Ukita; Kenji Anami (IEEE J. Solid State Circuits, 1991)

An 8 ns 4 Mb serial access memory. - Hirotada Kuriyama; Toshihiko Hirose; Shuji Murakami; Tomohisa Wada; Kore-aki Fujita; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1991)

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy. - Atsushi Ohba; Shigeki Ohbayashi; Toru Shiomi; Satoshi Takano; Kenji Anami; Hiroki Honda; Yoshiyuki Ishigaki; Masahiro Hatanaka; Shigeo Nagao; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)

A 21-mW 4-Mb CMOS SRAM for battery operation. - Shuji Murakami; Kore-aki Fujita; Motomu Ukita; Kazuhito Tsutsumi; Yasuo Inoue; Osamu Sakamoto; Motoi Ashida; Yasumasa Nishimura; Yoshio Kohno; Tadashi Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1991)

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's. - Motomu Ukita; Shuji Murakami; Tadato Yamagata; Hirotada Kuriyama; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1993)

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. - Toru Shiomi; Tomohisa Wada; Shigeki Ohbayashi; Atsushi Ohba; Hiroki Honda; Yoshiyuki Ishigaki; Shiro Hine; Kenji Anami; Kimio Suzuki; Tadashi Sumi (IEEE J. Solid State Circuits, 1993)

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. - Tadato Yamagata; Hirotoshi Sato; Kore-aki Fujita; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1996)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. - Hideyuki Noda; Kazunari Inoue; Hans Jürgen Mattausch; Tetsushi Koide; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)