Efficient Implementation of the Vector Operation on the Loop Structured Computer. - Kenji Ichijo; Yoshio Yoshioka (PDPTA, 2003)

Comprehensive Evaluation of Packet Flow Control Methods for a Ring Nework of Processors on Chip. - Akiko Narita; Kenji Ichijo; Yoshio Yoshioka (ACIS-ICIS, 2010)

CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and Analysis. - Tomoyuki Nagase; Kenji Ichijo; Akiko Narita; Yoshio Yoshioka (DFT, 2010)

Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System. - Tatsuya Suto; Kenji Ichijo; Yoshio Yoshioka (DFT, 2010)

Evaluation of Packet Flow Control Methods for a LSC on Chip with Hardware Requirements and Performance. - Akiko Narita; Kenji Ichijo; Yoshio Yoshioka (PDPTA, 2010)

Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate. - Hiroyuki Ogata; Kenji Ichijo; Kenji Kondo; Akito Hara (IEICE Trans. Electron., 2013)

Expansion of operations in a multicore dataflow DSP. - Kenji Ichijo; Sora Deguchi; Akiko Narita (ICCE-TW, 2016)

Evaluation of the Redundant Traffic Reduction Node Using the Packet Cache Coping with Different Byte Offsets among Streams. - Wataru Yokota; Kenji Ichijo; Akiko Narita (NaNA, 2016)

Autonomous Decision of Function of the Redundant Traffic Reduction Node Using a New IP Option. - Tomohiro Yoshida; Yamato Ikeda; Kenji Ichijo; Akiko Narita (NaNA, 2016)

Design of Multicore Dataflow DSPs with Different Loop Iteration Mechanisms. - Shun Orita; Akiko Narita; Kenji Ichijo (ICCE-TW, 2022)