An FPGA Solver for WSAT Algorithms. - Kenji Kanazawa; Tsutomu Maruyama (FPL, 2005)

Ab initio fragment molecular orbital (FMO) method applied to analysis of the ligand-protein interaction in a pheromone-binding protein. - Tadashi Nemoto; Dmitri G. Fedorov; Masami Uebayasi; Kenji Kanazawa; Kazuo Kitaura; Yuto Komeiji (Comput. Biol. Chem., 2005)

An FPGA Solver for Large SAT Problems. - Kenji Kanazawa; Tsutomu Maruyama (FPL, 2006)

An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma. - Yoshiki Yamaguchi; Kenji Kanazawa; Yoshiharu Ohke; Tsutomu Maruyama (ARC, 2007)

An FPGA Solver for Very Large SAT Problems. - Kenji Kanazawa; Tsutomu Maruyama (FPL, 2007)

An Approach for Solving Large SAT Problems on FPGA. - Kenji Kanazawa; Tsutomu Maruyama (ACM Trans. Reconfigurable Technol. Syst., 2010)

An FPGA Solver for SAT-Encoded Formal Verification Problems. - Kenji Kanazawa; Tsutomu Maruyama (FPL, 2011)

Electrochemically-switchable emission and absorption by using luminescent Lanthanide(III) complex and electrochromic molecule toward novel display device with dual emissive and reflective mode. - Kazuki Nakamura; Kenji Kanazawa; Norihisa Kobayashi (Displays, 2013)

FPGA acceleration of SAT/Max-SAT solving using variable-way cache. - Kenji Kanazawa; Tsutomu Maruyama (FPL, 2014)

High-Speed Calculation of Convex Hull in 2D Images Using FPGA. - Kenji Kanazawa; Kahori Kemmotsu; Yamato Mori; Noriyuki Aibe; Moritoshi Yasunaga (PARCO, 2015)

An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. - Shohei Sassa; Kenji Kanazawa; Shaowei Cai 001; Moritoshi Yasunaga (SIGARCH Comput. Archit. News, 2016)

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA. - Kenji Kanazawa; Tsutomu Maruyama (IEICE Trans. Inf. Syst., 2017)

FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT. - Kenji Kanazawa; Shaowei Cai 001 (MCSoC, 2018)

FPGA-Based Object Detection for Autonomous Driving System. - Kenichi Harada; Kenji Kanazawa; Moritoshi Yasunaga (FPT, 2019)

Accelerating Swap-Based Tabu Search for Solving Maximum Clique Problems on FPGA. - Kenji Kanazawa (ISPA/BDCloud/SocialCom/SustainCom, 2019)

FPGA Acceleration of Swap-Based Tabu Search for Solving Maximum Clique Problems. - Kenji Kanazawa (J. Inf. Process., 2022)

FPGA Implementation of Minimum Spanning Tree Calculation Towards Application for Capacitated Vehicle Routing Problems. - Jiheng Wang; Kenji Kanazawa; Moritoshi Yasunaga (ICCE, 2024)

A FPGA-based Learning Accelerator for Self-Organizing Map and Its Application to Trend-Visualization. - Yusuke Yamagiwa; Kenji Kanazawa; Moritoshi Yasunaga (ICCE, 2024)

A highly scalable Self-organizing Map accelerator on FPGA and its performance evaluation. - Yusuke Yamagiwa; Yuki Kawahara; Kenji Kanazawa; Moritoshi Yasunaga (Artif. Life Robotics, 2024)

FPGA Implementation of Sparse Matrix Vector Multiplication with Small-Scale Matrix Element Router. - Ryosuke Yanangisawa; Kenji Kanazawa (ICCE, 2025)

A Fast Savings Algorithm for Solving Large-Scale Euclidean CVRPs. - Kenji Kanazawa (ICCSA (Workshops 3), 2025)