An efficient algorithm for the euclidean distance transformation. - Toshihiro Kato; Tomio Hirata; Toyofumi Saito; Kenji Kise (Syst. Comput. Jpn., 1996)

DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations. - Ryo Takata; Kenji Kise; Hiroki Honda; Toshitsugu Yuba (IPDPS, 2002)

SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator. - Kenji Kise; Hiroki Honda; Toshitsugu Yuba (Asia-Pacific Computer Systems Architecture Conference, 2003)

FIBER: A Generalized Framework for Auto-tuning Software. - Takahiro Katagiri; Kenji Kise; Hiroaki Honda; Toshitsugu Yuba (ISHPC, 2003)

Effect of auto-tuning with user's knowledge for numerical software. - Takahiro Katagiri; Kenji Kise; Hiroki Honda; Toshitsugu Yuba (Conf. Computing Frontiers, 2004)

The SimCore/Alpha Functional Simulator. - Kenji Kise; Takahiro Katagiri; Hiroki Honda; Toshitsugu Yuba (WCAE, 2004)

Evaluation of the Acknowledgment Reduction in a Software-DSM System. - Kenji Kise; Takahiro Katagiri; Hiroki Honda; Toshitsugu Yuba (PPAM, 2005)

Towards scalable and simple software-DSM systems. - Kenji Kise; Takahiro Katagiri; Hiroki Honda; Toshitsugu Yuba (SOSP, 2005)

A time-to-live based reservation algorithm on fully decentralized resource discovery in Grid computing. - Sanya Tangpongprasit; Takahiro Katagiri; Kenji Kise; Hiroki Honda; Toshitsugu Yuba (Parallel Comput., 2005)

Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment. - Satoshi Ohshima; Kenji Kise; Takahiro Katagiri; Toshitsugu Yuba (VECPAR, 2006)

ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software. - Takahiro Katagiri; Kenji Kise; Hiroki Honda; Toshitsugu Yuba (Parallel Comput., 2006)

ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility. - Takahiro Katagiri; Kenji Kise; Hiroki Honda; Toshitsugu Yuba (Parallel Comput., 2006)

Introduction. - Kenji Kise; Toshinori Sato; Hironori Nakajo (SIGARCH Comput. Archit. News, 2007)

The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors. - Yosuke Mori; Kenji Kise (PDCAT, 2009)

A Study of an Infrastructure for Research and Development of Many-Core Processors. - Koh Uehara; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (PDCAT, 2009)

SimCell: A Processor Simulator for Multi-Core Architecture Research. - Shimpei Sato; Naoki Fujieda; Akira Moriya; Kenji Kise (Inf. Media Technol., 2009)

CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. - Takefumi Miyoshi; Kenji Kise; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2010)

Pattern-Based Systematic Task Mapping for Many-Core Processors. - Shintaro Sano; Masahiro Sano; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (ICNC, 2010)

Smart Core System for Dependable Many-Core Processor with Multifunction Routers. - Shinya Takamaeda; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (ICNC, 2010)

A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors. - Naoki Fujieda; Kenji Kise (ICNC, 2011)

Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. - Mochamad Asri; Naoki Fujieda; Kenji Kise (ISOCC, 2011)

CoreSymphony: an efficient reconfigurable multi-core architecture. - Tomoyuki Nagatsuka; Yoshito Sakaguchi; Takayuki Matsumura; Kenji Kise (SIGARCH Comput. Archit. News, 2011)

An FPGA-based scalable simulation accelerator for tile architectures. - Shinya Takamaeda-Yamazaki; Ryosuke Sasakawa; Yoshito Sakaguchi; Kenji Kise (SIGARCH Comput. Archit. News, 2011)

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. - Shinya Takamaeda-Yamazaki; Shintaro Sano; Yoshito Sakaguchi; Naoki Fujieda; Kenji Kise (ARC, 2012)

CoreSymphony architecture. - Tomoyuki Nagatsuka; Yoshito Sakaguchi; Kenji Kise (Conf. Computing Frontiers, 2012)

Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations. - Ryohei Kobayashi 001; Shinya Takamaeda-Yamazaki; Kenji Kise (ICNC, 2012)

Application Aware DRAM Bank Partitioning in CMP. - Takakazu Ikeda; Kenji Kise (ICPADS, 2013)

LEF: long edge first routing for two-dimensional mesh network on chip. - Ryosuke Sasakawa; Kenji Kise (NoCArc@MICRO, 2013)

The Ultrasmall soft processor. - Yuichiro Tanaka; Shimpei Sato; Kenji Kise (SIGARCH Comput. Archit. News, 2013)

An NoC-based evaluation platform for safety-critical automotive applications. - Tomohiro Yoneda; Masashi Imai; Hiroshi Saito; Takahiro Hanyu; Kenji Kise; Yuichi Nakamura 002 (APCCAS, 2014)

Ultrasmall: The smallest MIPS soft processor. - Hiroshi Nakatsuka; Yuichiro Tanaka; Thiem Van Chu; Shinya Takamaeda-Yamazaki; Kenji Kise (FPL, 2014)

flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. - Shinya Takamaeda-Yamazaki; Kenji Kise (FPL, 2014)

KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. - Thiem Van Chu; Shimpei Sato; Kenji Kise (MCSoC, 2014)

Design and Performance Evaluation of a Manycore Processor for Large FPGA. - Haruka Mori; Kenji Kise (MCSoC, 2014)

A framework for efficient rapid prototyping by virtually enlarging FPGA resources. - Shinya Takamaeda-Yamazaki; Kenji Kise (ReConFig, 2014)

ArchHDL: A Novel Hardware RTL Design Environment in C++. - Shimpei Sato; Kenji Kise (ARC, 2015)

A Challenge of Portable and High-Speed FPGA Accelerator. - Takuma Usui; Ryohei Kobayashi 001; Kenji Kise (ARC, 2015)

Dependable real-time task execution scheme for a many-core platform. - Tomohiro Yoneda; Masashi Imai; Hiroshi Saito; Kenji Kise (DFTS, 2015)

Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. - Thiem Van Chu; Shimpei Sato; Kenji Kise (FCCM, 2015)

Ultra-fast NoC emulation on a single FPGA. - Thiem Van Chu; Shimpei Sato; Kenji Kise (FPL, 2015)

A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors. - Yuki Matsuda 003; Ryosuke Sasakawa; Kenji Kise (CANDAR, 2015)

Effective Parallel Simulation of ArchHDL under Manycore Environment. - Tomohiro Misono; Ryohei Kobayashi 001; Shimpei Sato; Kenji Kise (CANDAR, 2015)

FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems. - Ryohei Kobayashi 001; Kenji Kise (MCSoC, 2015)

Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research. - Eri Ogawa; Yuki Matsuda 003; Tomohiro Misono; Ryohei Kobayashi 001; Kenji Kise (MCSoC, 2015)

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs. - Shinya Takamaeda-Yamazaki; Hiroshi Nakatsuka; Yuichiro Tanaka; Kenji Kise (IEICE Trans. Inf. Syst., 2015)

An Effective Page Padding Method for RAM Buffer Algorithms to Enhance the SSD Endurance. - Eri Ogawa; Kenji Kise (CANDAR, 2016)

A Cost-Effective and Scalable Merge Sorter Tree on FPGAs. - Takuma Usui; Thiem Van Chu; Kenji Kise (CANDAR, 2016)

The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. - Masashi Imai; Thiem Van Chu; Kenji Kise; Tomohiro Yoneda (NOCS, 2016)

A High-speed Verilog HDL Simulation Method using a Lightweight Translator. - Ryohei Kobayashi 001; Tomohiro Misono; Kenji Kise (SIGARCH Comput. Archit. News, 2016)

Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. - Susumu Mashimo; Thiem Van Chu; Kenji Kise (SIGARCH Comput. Archit. News, 2016)

High-Performance Hardware Merge Sorter. - Susumu Mashimo; Thiem Van Chu; Kenji Kise (FCCM, 2017)

Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip. - Thiem Van Chu; Myeonggu Kang; Shi Fa; Kenji Kise (MCSoC, 2017)

A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism. - Ryohei Kobayashi 001; Kenji Kise (IEICE Trans. Inf. Syst., 2017)

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. - Thiem Van Chu; Shimpei Sato; Kenji Kise (ACM Trans. Reconfigurable Technol. Syst., 2017)

A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath. - Makoto Saitoh; Elsayed A. Elsayed; Thiem Van Chu; Susumu Mashimo; Kenji Kise (FCCM, 2018)

An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs. - Thiem Van Chu; Kenji Kise (FPL, 2018)

Very Massive Hardware Merge Sorter. - Makoto Saitoh; Kenji Kise (FPT, 2018)

Swap Based Merge Network for High Performance Sorting Accelerators. - Kenji Kise (HEART, 2018)

An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem. - Yuuma Azuma; Hayato Sakagami; Kenji Kise (MCSoC, 2018)

Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records. - Elsayed A. Elsayed; Kenji Kise (MCSoC, 2018)

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment. - Shimpei Sato; Ryohei Kobayashi 001; Kenji Kise (IEICE Trans. Inf. Syst., 2018)

An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA. - Hiromu Miyazaki; Junya Miura; Kenji Kise (HEART, 2019)

Towards an Efficient Hardware Architecture for Odd-Even Based Merge Sorter. - Elsayed A. Elsayed; Kenji Kise (MCSoC, 2019)

An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA. - Katsunoshin Matsui; Md. Ashraful Islam; Kenji Kise (MCSoC, 2019)

LEF: An Effective Routing Algorithm for Two-Dimensional Meshes. - Thiem Van Chu; Kenji Kise (IEICE Trans. Inf. Syst., 2019)

Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs. - Thiem Van Chu; Kenji Kise; Kiyofumi Tanaka (FPGA, 2020)

A portable and Linux capable RISC-V computer system in Verilog HDL. - Junya Miura; Hiromu Miyazaki; Kenji Kise (CoRR, 2020)

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors. - Md. Ashraful Islam; Hiromu Miyazaki; Kenji Kise (CoRR, 2020)

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions. - Takuto Kanamori; Hiromu Miyazaki; Kenji Kise (CoRR, 2020)

High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter. - Elsayed A. Elsayed; Kenji Kise (IEICE Trans. Inf. Syst., 2020)

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining. - Hiromu Miyazaki; Takuto Kanamori; Md. Ashraful Islam; Kenji Kise (IEICE Trans. Inf. Syst., 2020)

A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA. - Fumio Hamanaka; Takuto Kanamori; Kenji Kise (MCSoC, 2021)

Efficient Resource Shared RISC-V Multicore Processor. - Md. Ashraful Islam; Kenji Kise (MCSoC, 2021)

RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions. - Takuto Kanamori; Kenji Kise (MCSoC, 2021)

A function-rich FPGA system of camera image processing for video meeting. - Takashi Odan; Takuto Kanamori; Kenji Kise (MCSoC, 2021)

An Efficient Resource Shared RISC-V Multicore Architecture. - Md. Ashraful Islam; Kenji Kise (IEICE Trans. Inf. Syst., 2022)

RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor. - Takuto Kanamori; Takashi Odan; Kazuki Hirohata; Kenji Kise (IEICE Trans. Inf. Syst., 2022)

Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators. - Md. Ashraful Islam; Kenji Kise (HEART, 2023)

An open-source and GUI-capable RISC-V computer system on a low-end FPGA board. - Kenji Kise (MCSoC, 2023)

A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs. - Yuji Yamada; Nesrine Berjab; Tomohiro Yoneda; Kenji Kise (MCSoC, 2023)

An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration. - Fumio Hamanaka; Takashi Odan; Kenji Kise; Thiem Van Chu (IEEE Access, 2023)