A 32 kbyte integrated cache memory. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Tsukasa Shirotori; Toshinari Takayanagi; Tetsuya Iizuka; Takeo Maeda; Jinichi Matsunaga; Hiromichi Fuji; Kenji Maeguchi; Kiyoshi Kobayashi; Tomoyuki Ando; et al. (IEEE J. Solid State Circuits, 1989)

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell. - Takayuki Ootani; Shigeyuki Hayakawa; Masakazu Kakumu; Akira Aona; Masaaki Kinugawa; Hideki Takeuchi; Kazuhiro Noguchi; Tomoaki Yabe; Katsuhiko Sato; Kenji Maeguchi; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1990)

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. - Junji Mori; Masato Nagamatsu; Masashi Hirano; Shigeru Tanaka; Makoto Noda; Yoshiaki Toyoshima; Kazuhiro Hashimoto; Hiroyuki Hayashida; Kenji Maeguchi (IEEE J. Solid State Circuits, 1991)

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network. - Kenji Sakaue; Yasuro Shobatake; Masahiko Motoyama; Yoshinari Kumaki; Satoru Takatsuka; Shigeru Tanaka; Hiroyuki Hara; Kouji Matsuda; Shuji Kitaoka; Makoto Noda; Youichiro Niitsu; Masayuki Norishima; et al. (IEEE J. Solid State Circuits, 1991)