A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. - Kazutaka Nogami; Takayasu Sakurai; Kazuhiro Sawada; Kenji Sakaue; Yuichi Miyazawa; Shinichi Tanaka; Ypocjo Hiruta; Katsuto Katoh; Toshinari Takayanagi; Tsukasa Shirotori; Yasuo Itoh; Masanori Uchida; et al. (IEEE J. Solid State Circuits, 1990)

A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture. - Yasuro Shobatake; Masahiko Motoyama; Emiko Shobatake; Takashi Kamitake; Shoichi Shimizu; Makoto Noda; Kenji Sakaue (IEEE J. Sel. Areas Commun., 1991)

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network. - Kenji Sakaue; Yasuro Shobatake; Masahiko Motoyama; Yoshinari Kumaki; Satoru Takatsuka; Shigeru Tanaka; Hiroyuki Hara; Kouji Matsuda; Shuji Kitaoka; Makoto Noda; Youichiro Niitsu; Masayuki Norishima; et al. (IEEE J. Solid State Circuits, 1991)