LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator. - Kenji Shimazaki; Hiroyuki Tsujikawa; Seijiro Kojima; Shouzou Hirano (ISQED, 2000)

A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification. - Hiroyulu Tsujikawa; Kenji Shimazaki; Shozo Hirano; Motohiro Ohki; Talcashi Yoneda; Hiroshi Benno (CICC, 2002)

An EMI-Noise Analysis on LSI Design with Impedance Estimation. - Kenji Shimazaki; Shouzou Hirano; Hiroyuki Tsujikawa (ISQED, 2002)

A substrate noise analysis methodology for large-scale mixed-signal ICs. - Wen Kung Chu; Nishath K. Verghese; Heayn-Jun Chol; Kenji Shimazaki; Hiroyuki Tsujikawa; Shouzou Hirano; Shirou Doushoh; Makoto Nagata; Atsushi Iwata; Takafumi Ohmoto (CICC, 2003)

A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation. - Hiroyuki Tsujikawa; Shozo Hirano; Kenji Shimazaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. - Shen Lin; Makoto Nagata; Kenji Shimazaki; Kazuhiro Satoh; Masaya Sumita; Hiroyuki Tsujikawa; Andrew T. Yang (CICC, 2004)

Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. - Yoshihide Komatsu; Koichiro Ishibashi; Masaharu Yamamoto; Toshiro Tsukada; Kenji Shimazaki; Mitsuya Fukazawa; Makoto Nagata (CICC, 2005)

An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. - Kenji Shimazaki; Mitsuya Fukazawa; Makoto Nagata; Shingo Miyahara; Masaaki Hirata; Kazuhiro Satoh; Hiroyuki Tsujikawa (CICC, 2005)

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. - Kenji Shimazaki; Makoto Nagata; Takeshi Okumoto; Shozo Hirano; Hiroyuki Tsujikawa (IEICE Trans. Electron., 2005)

Power-Supply Noise Reduction with Design for Manufacturability. - Hiroyuki Tsujikawa; Kenji Shimazaki; Shozo Hirano; Kazuhiro Sato; Masanori Hirofuji; Junichi Shimada; Mitsumi Ito; Kiyohito Mukai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. - Kenji Shimazaki; Makoto Nagata; Mitsuya Fukazawa; Shingo Miyahara; Masaaki Hirata; Kazuhiro Satoh; Hiroyuki Tsujikawa (IEICE Trans. Electron., 2006)

A minimum decap allocation technique based on simultaneous switching for nanoscale SoC. - Kenji Shimazaki; Takaaki Okumura (CICC, 2009)

Gate Delay Estimation in STA under Dynamic Power Supply Noise. - Takaaki Okumura; Fumihiro Minami; Kenji Shimazaki; Kimihiko Kuwada; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)