A 1.71-million transistor CMOS CPU chip with a testable cache architecture. - Yuichi Saito; Yukihiko Shimazu; Tom Shimizu; Kenji Shirai; Isao Fujioka; Yoshitetsu Nishiwaki; Junichi Hinata; Yoshiki Shimotsuma; Masayoshi Sakao (IEEE J. Solid State Circuits, 1993)

Estimation of Machining Accuracy by Measurement of Surface Texture Pattern. - Kouichi Tozawa; Naohito Toida; Yoshikazu Kobayashi; Kenji Shirai (Int. J. Autom. Technol., 2010)

Quantitative damage assessment of concrete structures based on 3D laser scanning. - Tomohiro Mizoguchi; Yasuhiro Koda; Yoshikazu Kobayashi; Ichiro Iwaki; Yasuhiko Hara; Kenji Shirai; Hwa-Soo Lee; Hiroyuki Wakabayashi (IGARSS, 2011)

Parts identification and motion estimation on CT scanned assembly meshes. - Tomohiro Mizoguchi; Yoshikazu Kobayashi; Kenji Shirai; Satoshi Kanai (SIGGRAPH Posters, 2011)

Generation and Assessment of Random Surface Texture over a Wide Area. - Yoshikazu Kobayashi; Kenji Shirai; Yasuhiko Hara; Tomohiro Mizoguchi; Kiyotaka Kawasaki (Int. J. Autom. Technol., 2011)