An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

New nibbled-page architecture for high-density DRAMs. - Kenji Numata; Yukihito Oowaki; Yasuo Itoh; Takahiko Hara; Kenji Tsuchida; Masako Ohta; Shigyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1989)

The stabilized reference-line (SRL) technique for scaled DRAMs. - Kenji Tsuchida; Yukihito Oowaki; Masako Ohta; Daisaburo Takashima; Shigeyoshi Watanabe; Kazuya Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Word-line architecture for highly reliable 64-Mb DRAM. - Daisaburo Takashima; Yukihito Oowaki; Ryu Ogiwara; Yohji Watanabe; Kenji Tsuchida; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1992)

Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro. - Tsuneo Inaba; Kenji Tsuchida; Tadahiko Sugibayashi; Shuichi Tahara; Hiroaki Yoda (CICC, 2003)

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. - Yoshihisa Iwata; Kenji Tsuchida; Tsuneo Inaba; Yui Shimizu; R. Takizawa; Yoshihiro Ueda; Tadahiko Sugibayashi; Yoshiaki Asao; Takeshi Kajiyama; Keiji Hosotani; Sumio Ikegawa; Tadashi Kai; et al. (ISSCC, 2006)

MRAM Write Error Categorization with QCKB. - Yuui Shimizu; Hisanori Aikawa; Keiji Hosotani; Naoharu Shimomura; Tadashi Kai; Yoshihiro Ueda; Yoshiaki Asao; Yoshihisa Iwata; Kenji Tsuchida; Sumio Ikegawa (MTDT, 2006)

A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory. - Yoshiaki Asao; Masayoshi Iwayama; Kenji Tsuchida; Akihiro Nitayama; Hiroaki Yoda; Hisanori Aikawa; Sumio Ikegawa; Tatsuya Kishi (DFT, 2008)

A 64Mb MRAM with clamped-reference and adequate-reference schemes. - Kenji Tsuchida; Tsuneo Inaba; Katsuyuki Fujita; Yoshihiro Ueda; Takafumi Shimizu; Yoshiaki Asao; Takeshi Kajiyama; Masayoshi Iwayama; Kuniaki Sugiura; Sumio Ikegawa; Tatsuya Kishi; Tadashi Kai; et al. (ISSCC, 2010)

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. - Kwangmyoung Rho; Kenji Tsuchida; Dongkeun Kim; Yutaka Shirai; Jihyae Bae; Tsuneo Inaba; Hiromi Noro; Hyunin Moon; Sungwoong Chung; Kazumasa Sunouchi; Jinwon Park; Kiseon Park; et al. (ISSCC, 2017)

A perspective on NVRAM technology for future computing system. - Katsuhiko Hoya; Kosuke Hatsuda; Kenji Tsuchida; Yohji Watanabe; Yusuke Shirota; Tatsunori Kanai (VLSI-DAT, 2019)