The Error Latency of Delay Faults in Combinational and Sequential Circuits. - Kenneth D. Wagner (ITC, 1985)

Pseudorandom Testing. - Kenneth D. Wagner; Cary K. Chin; Edward J. McCluskey (IEEE Trans. Computers, 1987)

Design for Testability of Mixed Signal Integrated Circuits. - Kenneth D. Wagner; Thomas W. Williams (ITC, 1988)

Clock system design. - Kenneth D. Wagner (IEEE Des. Test, 1988)

Probability models for pseudorandom test sequences. - Edward J. McCluskey; Samy Makar; Samiha Mourad; Kenneth D. Wagner (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Guest Editorial: The Many Faces of Test. - Kenneth D. Wagner (IEEE Des. Test Comput., 1990)

Enhancing Board Functional Self-Test by Concurrent Sampling. - Kenneth D. Wagner; Thomas W. Williams (ITC, 1991)

Testable Programmable Digital Clock Pulse Control Elements. - Kenneth D. Wagner; Bernd Könemann (ITC, 1993)

High-Level Synthesis for Testability: A Survey and Perspective. - Kenneth D. Wagner; Sujit Dey (DAC, 1996)

EIC Message. - Kenneth D. Wagner; Yervant Zorian (IEEE Des. Test Comput., 1996)

Design for Testability Techniques at the Behavioral and Register-Transfer Levels. - Sujit Dey; Anand Raghunathan; Kenneth D. Wagner (J. Electron. Test., 1998)

Robust Scan-Based Logic Test in VDSM Technologies. - Kenneth D. Wagner (Computer, 1999)

Keeping current with silicon and systems technology in the mid-90s. - Kenneth D. Wagner (IEEE Des. Test Comput., 2005)