Design validation of .18 μm 1 GHz cache and register arrays. - Doug Malone; Paul Bunce; Joe DellaPietro; John Davis; James Dawson; Thomas J. Knips; Don Plass; Phil Pritzlaff; Kenneth Reyer (CICC, 2000)

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; Michael A. Sperling; et al. (ISSCC, 2015)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)

A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology. - Noam Jungmann; R. Joshi; Elazar Kachir; K. Shimanovich; B. He; T. Cohen; T. Miller; D. Leu; Dinesh Kannambadi; I. Wagner; Kenneth Reyer; H. Konen; et al. (VLSI Technology and Circuits, 2023)