The Post Office-Communication Support for Distributed Ensemble Architectures. - Kenneth S. Stevens; Shane V. Robison; Alan L. Davis (ICDCS, 1986)

The Architecture of FAIM-1. - Judy M. Anderson; William S. Coates; Alan L. Davis; Robert W. Hon; Ian N. Robinson; Shane V. Robison; Kenneth S. Stevens (Computer, 1987)

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. - Wei-Chun Chou; Peter A. Beerel; Ran Ginosar; Rakefet Kol; Chris J. Myers; Shai Rotem; Ken S. Stevens; Kenneth Y. Yun (ASYNC, 1998)

A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications. - Bruce W. Hunt; Kenneth S. Stevens; Bruce W. Suter; Donald S. Gelosh (ASYNC, 1998)

RAPPID: An Asynchronous Instruction Length Decoder. - Shai Rotem; Ken S. Stevens; Charles Dike; Marly Roncken; Boris Agapiev; Ran Ginosar; Rakefet Kol; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun (ASYNC, 1999)

Relative Timing. - Ken S. Stevens; Shai Rotem; Ran Ginosar (ASYNC, 1999)

CAD Directions for High Performance Asynchronous Circuits. - Ken S. Stevens; Shai Rotem; Steven M. Burns; Jordi Cortadella; Ran Ginosar; Michael Kishinevsky; Marly Roncken (DAC, 1999)

Multirate as a hardware paradigm. - Bruce W. Suter; Kenneth S. Stevens; Scott R. Velazquez; Truong Q. Nguyen (ICASSP, 1999)

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. - Jordi Cortadella; Michael Kishinevsky; Steven M. Burns; Ken S. Stevens (ICCAD, 1999)

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. - Marly Roncken; Ken S. Stevens; Rajesh Pendurkar; Shai Rotem; Parimal Pal Chaudhuri (ASYNC, 2000)

Fsimac: a fault simulator for asynchronous sequential circuits. - Susmita Sur-Kolay; Marly Roncken; Ken S. Stevens; Parimal Pal Chaudhuri; Rob Roy (Asian Test Symposium, 2000)

An asynchronous instruction length decoder. - Kenneth S. Stevens; Shai Rotem; Ran Ginosar; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun; Rakefet Kol; Charles Dike; Marly Roncken (IEEE J. Solid State Circuits, 2001)

Relative Timing Based Verification of Timed Circuits and Systems. - Peter A. Beerel; Ken S. Stevens; Hoshik Kim (ASYNC, 2002)

Congruent Weak Conformance, a Partial Order among Processes. - Ronald W. Brower; Kenneth S. Stevens (FORTE, 2002)

Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. - Jordi Cortadella; Michael Kishinevsky; Steven M. Burns; Alex Kondratyev; Luciano Lavagno; Ken S. Stevens; Alexander Taubin; Alexandre Yakovlev (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Energy and Performance Models for Clocked and Asynchronous Communication. - Kenneth S. Stevens (ASYNC, 2003)

Relative timing [asynchronous design]. - Ken S. Stevens; Ran Ginosar; Shai Rotem (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Modeling and Verifying Circuits Using Generalized Relative Timing. - Sanjit A. Seshia; Randal E. Bryant; Kenneth S. Stevens (ASYNC, 2005)

Preface. - Ken S. Stevens; Sandeep K. Shukla; Montek Singh; Jean-Pierre Talpin (FMGALS@MEMOCODE, 2005)

Algorithms for MIS vector generation and pruning. - Kenneth S. Stevens; Florentin Dartu (ICCAD, 2006)

Dynamic gates with hysteresis and configurable noise tolerance. - Krishna Santhanam; Kenneth S. Stevens (VLSI-SoC, 2007)

Guest Editors' Introduction: GALS Design and Validation. - Michael Kishinevsky; Sandeep K. Shukla; Ken S. Stevens (IEEE Des. Test Comput., 2007)

Elastic Flow in an Application Specific Network-on-Chip. - Daniel Gebhardt; Kenneth S. Stevens (FMGALS@MEMOCODE, 2007)

Performance Evaluation of Elastic GALS Interfaces and Network Fabric. - JunBok You; Yang Xu 036; Hosuk Han; Kenneth S. Stevens (FMGALS@MEMOCODE, 2007)

The Family of 4-phase Latch Protocols. - Graham M. Birtwistle; Kenneth S. Stevens (ASYNC, 2008)

Network Simplicity for Latency Insensitive Cores. - Daniel Gebhardt; JunBok You; W. Scott Lee; Kenneth S. Stevens (NOCS, 2008)

Characterization of Asynchronous Templates for Integration into Clocked CAD Flows. - Kenneth S. Stevens; Yang Xu 036; Vikas S. Vij (ASYNC, 2009)

Automatic synthesis of computation interference constraints for relative timing verification. - Yang Xu 036; Ken S. Stevens (ICCD, 2009)

Power reduction through physical placement of asynchronous routers. - Daniel Gebhardt; Kenneth S. Stevens (NOCS, 2009)

The Future of Formal Methods and GALS Design. - Kenneth S. Stevens; Daniel Gebhardt; JunBok You; Yang Xu 036; Vikas S. Vij; Shomit Das; Krishnaji Desai (FMGALS@DATE, 2009)

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments. - David Barnhart; Tanya Vladimirova; Martin N. Sweeting; Kenneth S. Stevens (IEEE J. Solid State Circuits, 2009)

Concurrency Reduction of Untimed Latch Protocols - Theory and Practice. - Santosh N. Varanasi; Kenneth S. Stevens; Graham M. Birtwistle (ASYNC, 2010)

Control network generator for latency insensitive designs. - Eliyah Kilada; Kenneth S. Stevens (DATE, 2010)

Bandwidth optimization in asynchronous NoCs by customizing link wire length. - JunBok You; Daniel Gebhardt; Kenneth S. Stevens (ICCD, 2010)

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs. - Daniel Gebhardt; JunBok You; Kenneth S. Stevens (NOCS, 2010)

Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study. - Eliyah Kilada; Shomit Das; Kenneth S. Stevens (VLSI-SoC, 2010)

Design and Verification of Lazy and Hybrid Implementations of the SELF Protocol. - Eliyah Kilada; Kenneth S. Stevens (VLSI-SoC (Selected Papers), 2010)

Synchronous elasticization at a reduced cost: Utilizing the ultra simple fork and controller merging. - Eliyah Kilada; Kenneth S. Stevens (ICCAD, 2011)

Link pipelining strategies for an application-specific asynchronous NoC. - Daniel Gebhardt; JunBok You; Kenneth S. Stevens (NOCS, 2011)

Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems. - Ken S. Stevens; Alexandre Yakovlev (IET Comput. Digit. Tech., 2011)

Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs. - Daniel Gebhardt; JunBok You; Kenneth S. Stevens (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Energy and Performance Models for Synchronous and Asynchronous Communication. - Kenneth S. Stevens; Pankaj Golani; Peter A. Beerel (IEEE Trans. Very Large Scale Integr. Syst., 2011)

SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead. - Shomit Das; Vikas S. Vij; Kenneth S. Stevens (ASYNC, 2013)

Design of low energy, high performance synchronous and asynchronous 64-point FFT. - William Lee; Vikas S. Vij; Anthony R. Thatcher; Kenneth S. Stevens (DATE, 2013)

Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reduction. - Kenneth S. Stevens (ISPD, 2013)

Symbolic verification of timed asynchronous hardware protocols. - Krishnaji Desai; Kenneth S. Stevens; John O'Leary (ISVLSI, 2013)

A low power UART design based on asynchronous techniques. - Dipanjan Bhadra; Vikas S. Vij; Kenneth S. Stevens (MWSCAS, 2013)

Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm. - Shomit Das; Georgios Manetas; Kenneth S. Stevens; Roberto Suaya (NOCS, 2013)

Automatic addition of reset in asynchronous sequential control circuits. - Vikas S. Vij; Kenneth S. Stevens (VLSI-SoC, 2013)

Modelling Mixed 4phase Pipelines: Structures and Patterns. - Graham M. Birtwistle; Kenneth S. Stevens (ASYNC, 2014)

A Design Space and its Patterns: Modelling 2phase Asynchronous Pipelines. - Graham M. Birtwistle; Kenneth S. Stevens (HOWARD-60, 2014)

An a-FPGA architecture for relative timing based asynchronous designs. - Jotham Vaddaboina Manoranjan; Kenneth S. Stevens (ReConFig, 2014)

Interfacing Synchronous and Asynchronous Domains for Open Core Protocol. - Vikas S. Vij; Raghu Prasad Gudla; Kenneth S. Stevens (VLSID, 2014)

Qualifying Relative Timing Constraints for Asynchronous Circuits. - Jotham Vaddaboina Manoranjan; Kenneth S. Stevens (ASYNC, 2016)

Reconfigurable circuit for implementation of family of 4-phase latch protocols. - Jotham Vaddaboina Manoranjan; Kenneth S. Stevens (FPL, 2016)

Design of a multi-style and multi-frequency FPGA. - Jotham Vaddaboina Manoranjan; Solomon Surya Tej Mano Sajjan; Vivek B. Gujari; Kenneth S. Stevens (VLSI-SoC, 2016)

Path Based Timing Validation for Timed Asynchronous Design. - William Lee; Tannu Sharma; Kenneth S. Stevens (VLSID, 2016)

Timing Path-Driven Cycle Cutting for Sequential Controllers. - William Lee; Vikas S. Vij; Kenneth S. Stevens (ACM Trans. Design Autom. Electr. Syst., 2016)

Design of a low power, relative timing based asynchronous MSP430 microprocessor. - Dipanjan Bhadra; Kenneth S. Stevens (DATE, 2017)

Physical Design Variation in Relative Timed Asynchronous Circuits. - Tannu Sharma; Kenneth S. Stevens (ISVLSI, 2017)

A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols. - Mackenzie J. Wibbels; Shomit Das; Dheeraj Singh Takur; Venkata Nori; Kenneth S. Stevens (ASYNC, 2019)

Low Power SPI Design Based on Relative Timing Techniques. - Guillermo H. Makar; Francisco J. Badenas; Roberto G. Simone; Alejandro Furfaro; Kenneth S. Stevens; Roberto Suaya (ICECS, 2019)

Reducing Energy Consumption and Decentralizing Computing through Heat Redistribution. - Lincoln S. Stevens; Mackenzie J. Wibbels; Valerie A. Wilkinson; Kenneth S. Stevens (ASYNC, 2020)

Learning Based Timing Closure on Relative Timed Design. - Tannu Sharma; Sumanth Kolluru; Kenneth S. Stevens (VLSI-SoC (Selected Papers), 2020)

Automatic Timing Closure for Relative Timed Designs. - Tannu Sharma; Kenneth S. Stevens (VLSI-SOC, 2020)

Causal Path Identification for Timed and Sequential Circuits. - Mackenzie J. Wibbels; Kenneth S. Stevens (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling. - Venkata Nori; Baudouin Chauviere; Mackenzie J. Wibbels; Kenneth S. Stevens (ASYNC, 2023)

Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms. - Mackenzie J. Wibbels; Baudouin Chauviere; Kenneth S. Stevens (ASYNC, 2023)

Behavioral Simulation of Relative Timed Asynchronous Circuits. - Sumanth Kolluru; Kenneth S. Stevens (VLSI-SoC, 2024)

Timing Closure in Relative Timed Asynchronous Designs using Deep Reinforcement Learning. - Sumanth Kolluru; Kenneth S. Stevens (ASYNC, 2025)