Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. - Jafar Savoj; Kenny C.-H. Hsieh; Parag Upadhyaya; Fu-Tai An; Jay Im; Xuewen Jiang; Jalil Kamali; Kang Wei Lai; Zhaoyin Daniel Wu; Elad Alon; Ken Chang (CICC, 2012)

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. - Jafar Savoj; Kenny C.-H. Hsieh; Parag Upadhyaya; Fu-Tai An; Ade Bekele; Stanley Chen; Xuewen Jiang; Kang Wei Lai; Chi Fung Poon; Aman Sewani; Didem Turker; Karthik Venna; et al. (VLSIC, 2012)

A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. - Jafar Savoj; Kenny C.-H. Hsieh; Fu-Tai An; J. Gong; Jay Im; Xuewen Jiang; Anup P. Jose; Vassili Kireev; Siok-Wei Lim; Arianne Roldan; D. Z. Turker; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2013)

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. - Jafar Savoj; Hesam Amir Aslanzadeh; Declan Carey; Marc Erett; Wayne Fang; Yohan Frans; Kenny C.-H. Hsieh; Jay Im; Anup P. Jose; Didem Turker; Parag Upadhyaya; Zhaoyin Daniel Wu; et al. (CICC, 2014)

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. - Yohan Frans; Declan Carey; Marc Erett; Hesam Amir Aslanzadeh; Wayne Y. Fang; Didem Turker; Anup P. Jose; Adebabay Bekele; Jay Im; Parag Upadhyaya; Zhaoyin Daniel Wu; Kenny C.-H. Hsieh; et al. (IEEE J. Solid State Circuits, 2015)

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. - Chao-Chieh Li; Tsung-Hsien Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Kenny Hsieh; Mark Chen 001; Augusto Ronchini Ximenes; et al. (VLSI Circuits, 2016)

A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. - Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (CICC, 2017)

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. - Chao-Chieh Li; Min-Shueh Yuan; Chih-Hsien Chang; Yu-Tso Lin; Chia-Chun Liao; Kenny Hsieh; Mark Chen 001; Robert Bogdan Staszewski (ISSCC, 2017)

A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. - Ting-Kuei Kuan; Chin-Yang Wu; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2018)

A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. - Chen-Ting Ko; Ting-Kuei Kuan; Ruei-Pin Shen; Chih-Hsien Chang; Kenny Hsieh; Mark Chen 001 (VLSI Circuits, 2019)

A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET. - Dirk Pfaff; Shahaboddin Moazzeni; Leisheng Gao; Mei-Chen Chuang; Xin-Jie Wang; Chai Palusa; Robert Abbott; Rolando Ramirez; Maher Amer; Ming-Chieh Huang; Chih-Chang Lin; Fred Kuo; et al. (VLSI Circuits, 2019)

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. - Mao-Hsuan Chou; Ya-Tin Chang; Tsung-Hsien Tsai; Tsung-Che Lu; Chia-Chun Liao; Hung-Yi Kuo; Ruey-Bin Sheen; Chih-Hsien Chang; Kenny C.-H. Hsieh; Alvin Leng Sun Loke; Mark Chen 001 (VLSI Circuits, 2020)

A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications. - Tsung-Che Lu; Chin-Ming Fu; Chia-Chun Liao; Yu-Tso Lin; Chih-Hsien Chang; Kenny Hsieh (VLSI Circuits, 2021)

An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology. - Tsung-Che Lu; Chin-Ming Fu; Wei-Hsiang Wang; Fred Kuo; Chih-Hsien Chang; Kenny Hsieh; King-Ho Tam; Tze-Chiang Huang; Tom Chen 002; Mei Wong; Wei-pin Changchien; Frank Lee 004 (VLSI Technology and Circuits, 2024)