A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology. - Yu Jiang 004; Xu Liu 002; Xiwei Huang; Jing Guo; Mei Yan; Hao Yu 001; Jui-Cheng Huang; Kenny Cheng-Hsiang Hsieh; Tung-Tsun Chen (CICC, 2015)

A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package. - Mu-Shan Lin; Chien-Chun Tsai; Kenny Cheng-Hsiang Hsieh; Wen-Hung Huang; Yu-Chi Chen; Shu-Chun Yang; Chin-Ming Fu; Hao-Jie Zhan; Jinn-Yeh Chien; Shao-Yu Li; Y.-H. Chen; C.-C. Kuo; et al. (Hot Chips Symposium, 2016)

A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET. - Wei-Chih Chen; Shu-Chun Yang; Yu-Nan Shih; Wen-Hung Huang; Chien-Chun Tsai; Kenny Cheng-Hsiang Hsieh (VLSI Circuits, 2019)

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Tom Chen 002; Wen-Hung Huang; Jack Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (VLSI Circuits, 2019)

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Ching-Fang Chen; Wen-Hung Huang; Chi-Wei Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (IEEE J. Solid State Circuits, 2020)

3.8 A 0.65V 900µm² BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from -25°C to 125°C. - Bei-Shing Lien; Szu-Lin Liu; Wei-Lin Lai; Yi-Chen Lu; Yung-Chow Peng; Kenny Cheng-Hsiang Hsieh (ISSCC, 2024)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

4.6 A 0.8V, 31ppm/°C, -40dB DC-to-GHz Power-Supply-Rejection Standard-Vth Core-MOS-Only Voltage Reference with a 294µm2Area. - Bei-Shing Lien; Szu-Lin Liu; Wei-Lin Lai; Yi-Chen Lu; Yung-Chow Peng; Kenny Cheng-Hsiang Hsieh (ISSCC, 2025)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)