On-chip detection methodology for break-even time of power gated function units. - Kimiyoshi Usami; Yuya Goto; Kensaku Matsunaga; Satoshi Koyama; Daisuke Ikebuchi; Hideharu Amano; Hiroshi Nakamura (ISLPED, 2011)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. - Kimiyoshi Usami; Masaru Kudo; Kensaku Matsunaga; Tsubasa Kosaka; Yoshihiro Tsurui; Weihan Wang; Hideharu Amano; Hiroaki Kobayashi; Ryuichi Sakamoto; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ASP-DAC, 2014)

Design and evaluation of fine-grained power-gating for embedded microprocessors. - Masaaki Kondo; Hiroaki Kobayashi; Ryuichi Sakamoto; Motoki Wada; Jun Tsukamoto; Mitaro Namiki; Weihan Wang; Hideharu Amano; Kensaku Matsunaga; Masaru Kudo; Kimiyoshi Usami; Toshiya Komoda; et al. (DATE, 2014)