Field modifiable architecture with FPGAs and its design methodology. - Satoshi Komatsu; Yoshihisa Kojima; Hiroshi Saito; Kenshu Seto; Masahiro Fujita (FPT, 2002)

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. - Yoshihisa Kojima; Hiroshi Saito; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (IWLS, 2002)

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies. - Masahiro Fujita; Satoshi Komatsu; Hiroshi Saito; Kenshu Seto; Thanyapat Sakunkonchak; Yoshihisa Kojima (HICSS, 2003)

Engineering Changes in Field Modifiable Architectures. - Hiroshi Saito; Kenshu Seto; Yoshihisa Kojima; Satoshi Komatsu; Masahiro Fujita (MEMOCODE, 2003)

Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays. - Shanghua Gao; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (FPT, 2005)

Dynamically reconfigurable protocol transducer. - Shota Watanabe; Yuji Ishikawa; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (FPT, 2006)

Protocol Transducer Synthesis using Divide and Conquer approach. - Shigeru Watanabe; Kenshu Seto; Yuji Ishikawa; Satoshi Komatsu; Masahiro Fujita (ASP-DAC, 2007)

Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. - Shanghua Gao; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (IESS, 2007)

SAT-based resource binding for reducing critical path delays. - Kenshu Seto; Yuta Nonaka; Takuya Maruizumi; Yasuhiro Shiraki (FPL, 2008)

Custom Instruction Generation with High-Level Synthesis. - Kenshu Seto; Masahiro Fujita (SASP, 2008)

Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation. - Masahiro Fujita; Kenshu Seto; Thanyapat Sakunkonchak (J. Satisf. Boolean Model. Comput., 2008)

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures. - Shanghua Gao; Hiroaki Yoshida; Kenshu Seto; Satoshi Komatsu; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. - Kenshu Seto; Masahiro Fujita (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Loop Fusion with Outer Loop Shifting for High-level Synthesis. - Yuta Kato; Kenshu Seto (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Forwarding Unit Generation for Loop Pipelining in High-level Synthesis. - Shingo Kusakabe; Kenshu Seto (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Scalar Replacement with Polyhedral Model. - Kenshu Seto (IPSJ Trans. Syst. LSI Des. Methodol., 2018)

Small Memory Footprint Neural Network Accelerators. - Kenshu Seto; Hamid Nejatollahi; Jiyoung An; Sujin Kang; Nikil D. Dutt (ISQED, 2019)

Scalar Replacement with Circular Buffers. - Kenshu Seto (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

Shift Register Initialization in Scalar Replacement for Reducing Code Size. - Kenshu Seto (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Scalar replacement in the presence of multiple write accesses for high-level synthesis. - Kenshu Seto (DATE, 2021)

Proposal for Non-Volatilization of eFPGA Core. - Keizo Hiraga; Kenshu Seto; Kazuhiro Bessho; Masahiro Iida (COOL CHIPS, 2025)

Minimizing Local Interconnections to Reduce Chip Area in eFPGAs. - Kenshu Seto; Masahiro Iida (HEART, 2025)

Enhancing FPGA Routing Efficiency with Graph Neural Network-Based Congestion Prediction. - Kazuki Tokuishi; Motoki Amagasaki; Masato Kiyama; Kenshu Seto (HEART, 2025)

Proposal for Non-Volatilization of Logic Cell Architecture for eFPGA IP. - Keizo Hiraga; Kenshu Seto; Kazuhiro Bessho; Masahiro Iida (IPSJ Trans. Syst. LSI Des. Methodol., 2025)

Scalar Replacement in the Presence of Multiple Write Accesses with Non-constant Reuse Distances. - Kenshu Seto (IPSJ Trans. Syst. LSI Des. Methodol., 2025)