A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Dong-Jin Chang; Seung-Tak Ryu (A-SSCC, 2021)

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Gyeom-Je Bae; Dong-Hun Lee; Ye-Dam Kim; Hankyu Lee; Seong Joong Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. - Kent Edrian Lozada; Dong-Hun Lee; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2023)

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. - Bo Gao; Lizhen Zhang; Raymond Mabilangan; Chang-Un Park; Kent Edrian Lozada; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2024)

TID-Tolerant StrongARM Comparator and Sampling Network for Satellite Application High-Voltage ADCs. - Charlie Tahar; Changyeop Lee; Kun-Woo Park; Kent Edrian Lozada; Hyojun Kim; Ki-Ho Kwon; Seung-Tak Ryu (A-SSCC, 2024)

A 5× OSR 1MHz-BW 81dB-SNDR 5th-Order Noise-Shaping SAR ADC with Zero-Optimized 3rd-Order Integrator. - Lizhen Zhang; Bo Gao; Kun-Woo Park; Hyeongjin Kim; Kent Edrian Lozada; Ye-Dam Kim; Jianhui Wu 001; Seung-Tak Ryu (A-SSCC, 2024)

A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Chang-Un Park; Kun-Woo Park; Kwan-Hoon Song; Young-Hun Moon; Min-Jae Seo; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation. - Lizhen Zhang; Bo Gao; Kun-Woo Park; Kent Edrian Lozada; Raymond Mabilangan; Hyeongjin Kim; Jianhui Wu 001; Seung-Tak Ryu (IEEE Open J. Circuits Syst., 2024)

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. - Dong-Hun Lee; Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Ye-Dam Kim; Seung-Tak Ryu (CICC, 2025)

A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2025)