A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter. - Kenta Sogo; Akihiro Toya; Takamaro Kikkawa (ESSCIRC, 2012)

A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption. - Kenta Sogo; Akihiro Toya; Takamaro Kikkawa (ASP-DAC, 2013)

A 17 GHz bandwidth 1.2 mW CMOS switching matrix for UWB breast cancer imaging. - Afreen Azhari; Takumi Sugitani; Kenta Sogo; Takamaro Kikkawa; Xia Xiao (BioCAS, 2014)

CMOS equivalent time sampling of Gaussian monocycle pulse for confocal imaging. - Y. Seo; Kenta Sogo; Akihiro Toya; Takumi Sugitani; Afreen Azhari; X. Xiao; Takamaro Kikkawa (BioCAS, 2014)