A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A 1-Gb DRAM for file applications. - Tadahiko Sugibayashi; Isao Naritake; Satoshi Utsugi; Kentaro Shibahara; Ryuichi Oikawa; Hidemitsu Mori; Shouichi Iwao; Tatsunori Murotani; Kuniaki Koyama; Shinichi Fukuzawa; Toshiro Itani; Kunihiko Kasama; et al. (IEEE J. Solid State Circuits, 1995)

Reliable Threshold Voltage Determination for Sub-0.1µm Gate Length MOSFET's. - Morikazu Tsuno; Masato Suga; Masayasu Tanaka; Kentaro Shibahara; Mitiko Miura-Mattausch; Masataka Hirose (ASP-DAC, 1998)

Gate-Extension Overlap Control by Sb Tilt Implantation. - Kentaro Shibahara; Nobuhide Maeda (IEICE Trans. Electron., 2007)