Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. - Kentaroh Katoh; Abderrahim Doumar; Hideo Ito (IOLTS, 2005)

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. - Kentaroh Katoh; Hideo Ito (ETS, 2006)

Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. - Abderrahim Doumar; Kentaroh Katoh; Hideo Ito (DFT, 2007)

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

A Delay Measurement Technique Using Signature Registers. - Kentaroh Katoh; Toru Tanabe; Haque Md Zahidul; Kazuteru Namba; Hideo Ito (Asian Test Symposium, 2009)

Design for Delay Fault Testability of 2-Rail Logic Circuits. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (Asian Test Symposium, 2010)

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators. - Kentaroh Katoh; Yuta Doi; Satoshi Ito; Haruo Kobayashi 001; Ensi Li; Nobukazu Takai (Asian Test Symposium, 2013)

Digital Compensation for Timing Mismatches in Interleaved ADCs. - Ru Yi; Minghui Wu 008; Koji Asami; Haruo Kobayashi 001; Ramin Khatami; Atsuhiro Katayama; Isao Shimizu; Kentaroh Katoh (Asian Test Symposium, 2013)

A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. - Kentaroh Katoh; Yutaro Kobayashi; Takeshi Chujo; Junshan Wang; Ensi Li; Congbing Li; Haruo Kobayashi 001 (J. Electron. Test., 2014)

Analog/mixed-signal circuit design in nano CMOS era. - Haruo Kobayashi 001; Hitoshi Aoki; Kentaroh Katoh; Congbing Li (IEICE Electron. Express, 2014)

A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement. - Kentaroh Katoh; Kazuteru Namba (ISQED, 2015)

Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. - Kentaroh Katoh; Yutaro Kobayashi; Takeshi Chujo; Junshan Wang; Ensi Li; Congbing Li; Haruo Kobayashi 001 (J. Electron. Test., 2015)

High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. - Keno Sato; Takayuki Nakatani; Shogo Katayama; Daisuke Iimori; Gaku Ogihara; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Kazumi Hatayama; et al. (ATS, 2022)

Innovative Practices Track: Innovative Analog Circuit Testing Technologies. - Chris Mangelsdorf; Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán; Daisuke Iimori; Takayuki Nakatani; Shogo Katayama; Gaku Ogihara; Yujie Zhao; Jianglin Wei; Anna Kuwana; Kentaroh Katoh; et al. (VTS, 2022)

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. - Yujie Zhao; Kentaroh Katoh; Anna Kuwana; Shogo Katayama; Jianglin Wei; Haruo Kobayashi 001; Takayuki Nakatani; Kazumi Hatayama; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa (J. Electron. Test., 2022)

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. - Kentaroh Katoh; Shuhei Yamamoto; Zheming Zhao; Yujie Zhao; Shogo Katayama; Anna Kuwana; Takayuki Nakatani; Kazumi Hatayama; Haruo Kobayashi 001; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; et al. (ITC-Asia, 2023)

Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. - Keno Sato; Takayuki Nakatani; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Shogo Katayama; Daisuke Iimori; Misaki Takagi; Yujie Zhao; Shuhei Yamamoto; Anna Kuwana; Kentaroh Katoh; et al. (ITC, 2023)

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. - Shogo Katayama; Takayuki Nakatani; Daisuke Iimori; Misaki Takagi; Yujie Zhao; Anna Kuwana; Keno Sato; Takashi Ishida 003; Toshiyuki Okamoto; Tamotsu Ichikawa; Kentaroh Katoh; Kazumi Hatayama; et al. (IEICE Electron. Express, 2023)

A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA. - Kentaroh Katoh; Toru Nakura; Haruo Kobayashi 001 (DATE, 2025)