A statistical gate delay model for intra-chip and inter-chip variabilities. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ASP-DAC, 2003)

A Statistical Gate-Delay Model Considering Intra-Gate Variability. - Ken-ichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ICCAD, 2003)

Statistical modeling of gate-delay variation with consideration of intra-gate variability. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ISCAS (5), 2003)

Statistical Gate-Delay Modeling with Intra-Gate Variability. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)