An integrated approach to timing-driven synthesis and placement of arithmetic circuits. - Keoncheol Shin; Taewhan Kim 001 (ASP-DAC, 2004)

Leakage power minimization for the synthesis of parallel multiplier circuits. - Keoncheol Shin; Taewhan Kim 001 (ACM Great Lakes Symposium on VLSI, 2004)

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. - Keoncheol Shin; Taewhan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Restructuring field layouts for embedded memory systems. - Keoncheol Shin; Jungeun Kim; Seonggun Kim; Hwansoo Han (DATE, 2006)

Layout Transformations for Heap Objects Using Static Access Patterns. - Jinseong Jeon; Keoncheol Shin; Hwansoo Han (CC, 2007)

Abstracting access patterns of dynamic memory using regular expressions. - Jinseong Jeon; Keoncheol Shin; Hwansoo Han (ACM Trans. Archit. Code Optim., 2009)

Composition-based Cache simulation for structure reorganization. - Keoncheol Shin; Hwansoo Han; Kwang-Moo Choe (J. Syst. Archit., 2010)