A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Jinhyung Lee; Kyungjun Cho; Ji Hwan Park; Junil Moon; Sung-Hak Lee; Tae-Kyun Kim 001; Sanghoon Oh; Seokwoo Choi; Yongsuk Choi; Ho Sung Cho; Tae-Sik Yun; et al. (IEEE J. Solid State Circuits, 2023)

D3T: Distinctive Dual-Domain Teacher Zigzagging Across RGB-Thermal Gap for Domain-Adaptive Object Detection. - Dinh Phat Do; Taehoon Kim; Jaemin Na; Jiwon Kim; Keonho Lee; Kyunghwan Cho; Wonjun Hwang (CVPR, 2024)

13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. - Jaehyeok Yang; Hyeongjun Ko; Kyunghoon Kim; Hyunsu Park; Jihwan Park; Ji-Hyo Kang; Jin-Youp Cha; Seongjin Kim; Youngtaek Kim; Minsoo Park; Gangsik Lee; Keonho Lee; et al. (ISSCC, 2024)

Sparse Structure Exploration and Re-optimization for Vision Transformer. - Sangho An; Jinwoo Kim; Keonho Lee; Jingang Huh; Chanwoong Kwak; Yujin Lee; Moonsub Jin; Jangho Kim (UAI, 2025)