MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. - Biying Xu; Keren Zhu 001; Mingjie Liu; Yibo Lin; Shaolan Li; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2019)

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. - Keren Zhu 001; Mingjie Liu; Yibo Lin; Biying Xu; Shaolan Li; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2019)

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. - Mingjie Liu; Wuxi Li; Keren Zhu 001; Biying Xu; Yibo Lin; Linxiao Shen; Xiyuan Tang; Nan Sun 001; David Z. Pan (ASP-DAC, 2020)

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. - Mingjie Liu; Keren Zhu 001; Xiyuan Tang; Biying Xu; Wei Shi 011; Nan Sun 001; David Z. Pan (DAC, 2020)

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. - Mingjie Liu; Keren Zhu 001; Jiaqi Gu 002; Linxiao Shen; Xiyuan Tang; Nan Sun 001; David Z. Pan (DATE, 2020)

An Efficient Training Framework for Reversible Neural Architectures. - Zixuan Jiang; Keren Zhu 001; Mingjie Liu; Jiaqi Gu 002; David Z. Pan (ECCV (27), 2020)

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. - Keren Zhu 001; Hao Chen 059; Mingjie Liu; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2020)

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. - Hao Chen 059; Keren Zhu 001; Mingjie Liu; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2020)

Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network. - Keren Zhu 001; Mingjie Liu; Hao Chen 059; Zheng Zhao 003; David Z. Pan (MLCAD, 2020)

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. - Hao Chen 059; Mingjie Liu; Xiyuan Tang; Keren Zhu 001; Abhishek Mukherjee; Nan Sun 001; David Z. Pan (CICC, 2021)

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. - Hao Chen 059; Keren Zhu 001; Mingjie Liu; Xiyuan Tang; Nan Sun 001; David Z. Pan (DAC, 2021)

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. - Mingjie Liu; Xiyuan Tang; Keren Zhu 001; Hao Chen 059; Nan Sun 001; David Z. Pan (ICCAD, 2021)

Optimizer Fusion: Efficient Training with Better Locality and Parallelism. - Zixuan Jiang; Jiaqi Gu 002; Mingjie Liu; Keren Zhu 001; David Z. Pan (CoRR, 2021)

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. - Hao Chen 059; Mingjie Liu; Biying Xu; Keren Zhu 001; Xiyuan Tang; Shaolan Li; Yibo Lin; Nan Sun 001; David Z. Pan (IEEE Des. Test, 2021)

Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). - Keren Zhu 001; Hao Chen 059; Mingjie Liu; David Z. Pan (ASP-DAC, 2022)

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. - Keren Zhu 001; Hao Chen 059; Mingjie Liu; Xiyuan Tang; Wei Shi 011; Nan Sun 001; David Z. Pan (ASP-DAC, 2022)

Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). - Ahmet Faruk Budak; Zixuan Jiang; Keren Zhu 001; Azalia Mirhoseini; Anna Goldie; David Z. Pan (ASP-DAC, 2022)

TAG: Learning Circuit Spatial Embedding from Layouts. - Keren Zhu 001; Hao Chen 059; Walker J. Turner; George F. Kokai; Po-Hsuan Wei; David Z. Pan; Haoxing Ren (ICCAD, 2022)

Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. - Hanqing Zhu; Keren Zhu 001; Jiaqi Gu 002; Harrison Jin; Ray T. Chen; Jean Anne C. Incorvia; David Z. Pan (ICCAD, 2022)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. - Hao Chen 059; Walker J. Turner; Sanquan Song; Keren Zhu 001; George F. Kokai; Brian Zimmer; C. Thomas Gray; Brucek Khailany; David Z. Pan; Haoxing Ren (ISPD, 2022)

Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. - Ahmet Faruk Budak; Keren Zhu 001; David Z. Pan (ICCAD, 2023)

AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. - Zehua Pei; Fangzhou Liu; Zhuolun He; Guojin Chen; Haisheng Zheng; Keren Zhu 001; Bei Yu 001 (ICCAD, 2023)

Reinforcement Learning Guided Detailed Routing for Custom Circuits. - Hao Chen 059; Kai-Chieh Hsu; Walker J. Turner; Po-Hsuan Wei; Keren Zhu 001; David Z. Pan; Haoxing Ren (ISPD, 2023)

Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities. - Ahmet Faruk Budak; Keren Zhu 001; Hao Chen 059; Souradip Poddar; Linran Zhao; Yaoyao Jia; David Z. Pan (ISPD, 2023)

Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow. - Keren Zhu 001; Hao Chen 059; Mingjie Liu; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System. - Keren Zhu 001; Hao Chen 059; Mingjie Liu; David Z. Pan (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An In-Memory-Computing Charge-Domain Ternary CNN Classifier. - Xiangxing Yang; Keren Zhu 001; Xiyuan Tang; Meizhi Wang; Mingtao Zhan; Nanshu Lu; Jaydeep P. Kulkarni; David Z. Pan; Yongpan Liu; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. - Hyunsu Chae; Keren Zhu 001; Bhyrav Mutnury; Zixuan Jiang; Daniel De Araujo; Douglas Wallace; Douglas Winterberg; Adam R. Klivans; David Z. Pan (ASPDAC, 2024)

A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). - Ruiyu Lyu; Yuan Meng; Aidong Zhao; Zhaori Bi; Keren Zhu 001; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). - Peng Xu; Jintao Li; Tsung-Yi Ho; Bei Yu 001; Keren Zhu 001 (ASPDAC, 2024)

Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation. - Peng Xu; Guojin Chen; Keren Zhu 001; Tinghuan Chen; Tsung-Yi Ho; Bei Yu 001 (DAC, 2024)

A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing. - Souradip Poddar; Ahmet Faruk Budak; Linran Zhao; Chen-Hao Hsu; Supriyo Maji; Keren Zhu 001; Yaoyao Jia; David Z. Pan (DATE, 2024)

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. - Jintao Li; Haochang Zhi; Ruiyu Lyu; Wangzhen Li; Zhaori Bi; Keren Zhu 001; Yanhan Zeng; Weiwei Shan; Changhao Yan; Fan Yang 001; Yun Li 002; Xuan Zeng 001 (ICCAD, 2024)

Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis. - Ruiyu Lyu; Aidong Zhao; Yuan Meng; Keren Zhu 001; Zhaori Bi; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ICCAD, 2024)

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. - Hongyang Pan; Cunqing Lan; Yiting Liu; Zhiang Wang; Li Shang; Xuan Zeng 001; Fan Yang 001; Keren Zhu 001 (ICCAD, 2024)

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. - Yu Zhang 189; Yuan Pu 001; Fangzhou Liu; Peiyu Liao; Kai-Yuan Chao; Keren Zhu 001; Yibo Lin; Bei Yu 001 (ISPD, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation. - Guojin Chen; Keren Zhu 001; Seunggeun Kim; Hanqing Zhu; Yao Lai; Bei Yu 001; David Z. Pan (CoRR, 2024)

ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. - Hyunsu Chae; Keren Zhu 001; Bhyrav Mutnury; Douglas Wallace; Douglas Winterberg; Daniel De Araujo; Jay Reddy; Adam R. Klivans; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis. - Hongyang Pan; Keren Zhu 001; Fan Yang 001; Zhufei Chu; Xuan Zeng 001 (DATE, 2025)

DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement. - Chuyu Wang; Ke Hu; Fan Yang 001; Keren Zhu 001; Xuan Zeng 001 (DATE, 2025)

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. - Yuan Pu 001; Fangzhou Liu; Zhuolun He; Keren Zhu 001; Rongliang Fu; Ziyi Wang 010; Tsung-Yi Ho; Bei Yu 001 (ISPD, 2025)