First-order incremental block-based statistical timing analysis. - Chandramouli Visweswariah; K. Ravindran; Kerim Kalafala; Steven G. Walker; S. Narayan (DAC, 2004)

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. - Jochen A. G. Jess; Kerim Kalafala; Srinath R. Naidu; Ralph H. J. M. Otten; Chandramouli Visweswariah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

First-Order Incremental Block-Based Statistical Timing Analysis. - Chandramouli Visweswariah; K. Ravindran; Kerim Kalafala; Steven G. Walker; S. Narayan; Daniel K. Beece; Jeff Piaget; Natesan Venkateswaran; Jeffrey G. Hemmett (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Prototype for a large-scale static timing analyzer running on an IBM Blue Gene. - Akintayo Holder; Christopher D. Carothers; Kerim Kalafala (IPDPS Workshops, 2010)

A distributed timing analysis framework for large designs. - Tsung-Wei Huang; Martin D. F. Wong; Debjit Sinha; Kerim Kalafala; Natesan Venkateswaran (DAC, 2016)

Practical statistical static timing analysis with current source models. - Debjit Sinha; Vladimir Zolotov; Sheshashayee K. Raghunathan; Michael H. Wood; Kerim Kalafala (DAC, 2016)