Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits. - Kerry S. Lowe; P. Glenn Gulak (ICCAD, 1993)

A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits. - Kerry S. Lowe; P. Glenn Gulak (EURO-DAC, 1994)

A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch. - Kerry S. Lowe (IEEE J. Solid State Circuits, 1997)

Bufferless broadcasting: a low power distributed circuit technique for broadcasting 10-Gb/s chip input signals. - Kerry S. Lowe (IEEE J. Solid State Circuits, 1997)

A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. - Kerry S. Lowe; P. Glenn Gulak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)