Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. - Yasuo Sugure; Seiji Takeuchi; Yuichi Abe; Hiromichi Yamada; Kazuya Hirayanagi; Akihiko Tomita; Kesami Hagiwara; Takeshi Kataoka; Takanori Shimura (IEICE Trans. Electron., 2006)

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. - Kesami Hagiwara; Tomoichi Hayashi; Shumpei Kawasaki; Fumio Arakawa; Oleg Endo; Hayato Nomura; Akira Tsukamoto; Duong Nguyen; Binh Nguyen; Anh Tran; Hoan Hyunh; Ikuo Kudoh; et al. (COOL CHIPS, 2018)