Functional test generation based on word-level SAT. - Zhihong Zeng; Kesava R. Talupuru; Maciej J. Ciesielski (J. Syst. Archit., 2005)

Simulation Acceleration with HW Re-Compilation Avoidance. - Kyuho Shim; Kesava R. Talupuru; Maciej J. Ciesielski; Seiyang Yang (VLSI Design, 2008)

Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking. - Kesava R. Talupuru; Sanjai Athi (MTV, 2011)