A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). - David Jefferson; Srinivas Reddy; Christopher Lane; Ninh Ngo; Wanli Chang 003; Manuel Mijia; Ketan Zaveri; Cameron McClintock; Richard Cliff (FPGA, 1998)

A next generation architecture optimized for high density system level integration. - Richard Cliff; Srinivas Reddy; Cameron McClintock; David Jefferslon; Christopher Lane; Ketan Zaveri; Manuel Mejia; Andy Lee; Ninh Ngo; Risa Altaf; Bruce Pedersen; Frank Heile; et al. (CICC, 1999)