A 915 MHz, 499 μW, -99 dBm, and 100 kbps BFSK Direct Conversion Receiver. - Keun-Mok Kim; Eui-Rim Jeong; Kyung-Sik Choi; Subin Kim; Byeonghun Yun; Hyunki Jung; Wonkab Oh; Jinho Ko; Sang-Gug Lee 001 (ESSCIRC, 2019)

A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μW ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. - Kyung-Sik Choi; Keun-Mok Kim; Jinho Ko; Sang-Gug Lee 001 (A-SSCC, 2020)

29.7 A 490GHz 32mW Fully Integrated CMOS Receiver Adopting Dual-Locking FLL. - Kyung-Sik Choi; Dzuhri Radityo Utomo; Keun-Mok Kim; Byeonghun Yun; Sang-Gug Lee 001; In-Young Lee (ISSCC, 2020)

0.6 V 8.1/0.2µW Ultra-Low-Power Logarithmic Power Detectors Employing Subthreshold MOS Transistors. - Keun-Mok Kim; Hyun-Gi Seok; Jeong-Il Seo; Kyung-Sik Choi; Sang-Gug Lee 001 (A-SSCC, 2021)

A Sub-nW Single-Supply 32-kHz Sub-Harmonic Pulse Injection Crystal Oscillator. - Keun-Mok Kim; Subin Kim; Kyung-Sik Choi; Hyunki Jung; Jinho Ko; Sang-Gug Lee 001 (IEEE J. Solid State Circuits, 2021)

A -123-dBm Sensitivity Split-Channel BFSK Reconfigurable Data/Wake-Up Receiver for Low-Power Wide-Area Networks. - Keun-Mok Kim; Hyun-Gi Seok; Oh-Yong Jung; Kyung-Sik Choi; Byeonghun Yun; Subin Kim; Wonkab Oh; Eui-Rim Jeong; Jinho Ko; Sang-Gug Lee 001 (IEEE J. Solid State Circuits, 2021)

A Low-Noise and Fast-Settling UHF RFID Receiver With Digitally Controlled Leakage Cancellation. - Subin Kim; Kyung-Sik Choi; Keun-Mok Kim; Jinho Ko; Jusung Kim; Sang-Gug Lee 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up Receiver. - Keun-Mok Kim; Kyung-Sik Choi; Hyunki Jung; Byeonghun Yun; Subin Kim; Wonkab Oh; Eui-Soo Lee; Sujin Park; Eui-Rim Jeong; Jinho Ko; Sang-Gug Lee 001 (ISSCC, 2022)

A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA. - Kyung-Sik Choi; Jinho Ko; Keun-Mok Kim; Jusung Kim; Sang-Gug Lee 001 (IEEE J. Solid State Circuits, 2022)

A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration. - Kyung-Sik Choi; Keun-Mok Kim; Jinho Ko; Sang-Gug Lee 001 (IEEE J. Solid State Circuits, 2022)

A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL. - Kyung-Sik Choi; Keun-Mok Kim; Dzuhri Radityo Utomo; In-Young Lee; Sang-Gug Lee 001 (IEEE J. Solid State Circuits, 2022)

CMOS Fractional-N Frequency Synthesizer for UHF RFID Reader Applications With Transformer-Based ISF Manipulation VCO. - Hyunki Jung; Kyung-Sik Choi; Keun-Mok Kim; Daehoon Jo; Jaeheon Lee; Jusung Kim; Jinho Ko; Sang-Gug Lee 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency. - Keun-Mok Kim; Kyung-Sik Choi; Hyunki Jung; Byeonghun Yun; Jinglong Xu; Jinho Ko; Sang-Gug Lee 001 (IEEE J. Solid State Circuits, 2023)

A 24% Efficient, 15.36 dBm Output Power, Multi-Standard Digital Polar Transmitter with 7-bit Phase Interpolator-based BFSK Modulator and 23 dB Sidelobe Suppressed PA for Low-Power Wide Area Networks. - Hafiz Usman Mahmood; Keun-Mok Kim; Thinh Tran-Dinh; Jinglong Xu; Abdul Qahir; Jinho Ko; Jusung Kim; Sang-Gug Lee 001; Kyung-Sik Choi (A-SSCC, 2024)