A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process. - Keun-Seon Ahn; Jaewoo Park; Changsik Yoo (Int. J. Circuit Theory Appl., 2015)

A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process. - Keun-Seon Ahn; Changsik Yoo (Int. J. Circuit Theory Appl., 2015)