A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique. - Keun-Yong Chung; Kwang-Hyun Baek; Bo-Kyong Choi (ISOCC, 2021)

A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier. - Dong-Hyun Yoon; Dong-Kyu Jung; Kiho Seong; Jae-Soub Han; Keun-Yong Chung; Ju Eon Kim; Tony Tae-Hyoung Kim; Kwang-Hyun Baek (IEEE Trans. Very Large Scale Integr. Syst., 2022)

8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation. - Keun-Yong Chung; Honggu Kim; Yerim An; Kiho Seong; Dong-Hyun Shin; Kwang-Hyun Baek; Yong Shim (IEEE Access, 2024)