A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques. - Keunsoo Song; Sangkwon Lee; Dongkyun Kim; Youngbo Shim; Sangil Park; Bokrim Ko; Duckhwa Hong; Yongsuk Joo; Wooyoung Lee; Yongdeok Cho; Wooyeol Shin; Jaewoong Yun; et al. (CICC, 2014)

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications. - Hae-Kang Jung; Jaemo Yang; Jeonghun Lee; Hyeongjun Ko; Hyuk Lee; Taeksang Song; Jongjoo Shim; Sangkwon Lee; Keunsoo Song; Dongkyun Kim; Hyungsoo Kim; Yunsaing Kim (VLSIC, 2015)

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques. - Keunsoo Song; Sangkwon Lee; Dongkyun Kim; Youngbo Shim; Sangil Park; Bokrim Ko; Duckhwa Hong; Yongsuk Joo; Wooyoung Lee; Yongdeok Cho; Wooyeol Shin; Jaewoong Yun; et al. (IEEE J. Solid State Circuits, 2015)

A 2.3-mW 0.01-mm2 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS. - Yongjo Kim; Keunsoo Song; Dongkyun Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2017)