Variance reduction using wafer patterns in I_ddQ data. - W. Robert Daasch; James McNames; Daniel Bockelman; Kevin Cota (ITC, 2000)

Neighbor selection for variance reduction in I_DDQ and other parametric data. - W. Robert Daasch; Kevin Cota; James McNames; Robert Madge (ITC, 2001)

Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data. - W. Robert Daasch; Kevin Cota; James McNames; Robert Madge (ITC, 2002)

Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies. - Robert Madge; Manu Rehani; Kevin Cota; W. Robert Daasch (VTS, 2002)

Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort. - W. Robert Daasch; James McNames; Robert Madge; Kevin Cota (IEEE Des. Test Comput., 2002)

Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ. - Chris Schuermyer; Brady Benware; Kevin Cota; Robert Madge; W. Robert Daasch; L. Ning (ITC, 2003)

Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis. - Chris Schuermyer; Kevin Cota; Robert Madge; Brady Benware (ITC, 2005)