A Robust Solution to the Timing Convergence Problem in High-Performance Design. - Narendra V. Shenoy; Mahesh A. Iyer; Robert F. Damiano; Kevin Harer; Hi-Keung Tony Ma; Paul Thilking (ICCD, 1999)

Smart Simulation Using Collaborative Formal and Simulation Engines. - Pei-Hsin Ho; Thomas R. Shiple; Kevin Harer; James H. Kukula; Robert F. Damiano; Valeria Bertacco; Jerry Taylor; Jiang Long (ICCAD, 2000)

Supporting sequential assumptions in hybrid verification. - Eduard Cerny; Ashvin Dsouza; Kevin Harer; Pei-Hsin Ho; Hi-Keung Tony Ma (ASP-DAC, 2005)

Learning from Constraints for Formal Property Checking. - In-Ho Moon; Kevin Harer (J. Electron. Test., 2010)

Formal methods for coverage analysis of architectural power states in power-managed designs. - Aritra Hazra; Pallab Dasgupta; Ansuman Banerjee; Kevin Harer (ASP-DAC, 2012)

Abstraction-Based Livelock/Deadlock Checking for Hardware Verification. - In-Ho Moon; Kevin Harer (DIFTS@FMCAD, 2013)

POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent. - Aritra Hazra; Rajdeep Mukherjee; Pallab Dasgupta; Ajit Pal; Kevin Harer; Ansuman Banerjee; Subhankar Mukherjee 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)